GR712RC-UM, Jun 2017, Version 2.9 84 www.cobham.com/gaisler
GR712RC
9.6.8 AHB trace buffer index register
The AHB trace buffer index register contains the address of the next trace line to be written.
31:4 Trace buffer index counter (INDEX). Note that the number of bits actually implemented depends on the size of the
trace buffer.
9.6.9 AHB trace buffer breakpoint registers
The DSU contains two breakpoint registers for matching AHB addresses. A breakpoint hit is used to
freeze the trace buffer by automatically clearing the enable bit. Freezing can be delayed by program-
ming the DCNT field in the trace buffer control register to a non-zero value. In this case, the DCNT
value will be decremented for each additional trace until it reaches zero, after which the trace buffer is
frozen. A mask register is associated with each breakpoint, allowing breaking on a block of addresses.
Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detec-
tion. To break on AHB load or store accesses, the LD and/or ST bits should be set.
[31:2]: Breakpoint address (bits 31:2)
[31:2]: Breakpoint mask (see text)
[1]: LD - break on data load address
[0]: ST - beak on data store address
9.6.10 Instruction trace control register
The instruction trace control register contains a pointer that indicates the next line of the instruction
trace buffer to be written.
[15:0] Instruction trace pointer. Note that the number of bits actually implemented depends on the size of the trace buffer.
Figure 50. AHB trace buffer index register
03
31
INDEX
4
0000
01231
LD
BADDR[31:2]
Break address reg.
0231
ST
BMASK[31:2]
Break mask reg.
Figure 51. Trace buffer breakpoint registers
0
1
0
Figure 52. Instruction trace control register
0
31
RESERVED
IT POINTER
16
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