COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 201 www.cobham.com/gaisler
GR712RC
26.9.1 Interrupt registers
The interrupt registers give complete freedom to the software, by providing means to mask interrupts,
clear interrupts, force interrupts and read interrupt status.
When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set. The normal
sequence to initialize and handle a module interrupt is:
• Set up the software interrupt-handler to accept an interrupt from the module.
• Read the Pending Interrupt Register to clear any spurious interrupts.
• Initialize the Interrupt Mask Register, unmasking each bit that should generate the module inter-
rupt.
• When an interrupt occurs, read the Pending Interrupt Status Register in the software interrupt-
handler to determine the causes of the interrupt.
• Handle the interrupt, taking into account all causes of the interrupt.
• Clear the handled interrupt using Pending Interrupt Clear Register.
Masking interrupts: After reset, all interrupt bits are masked, since the Interrupt Mask Register is zero.
To enable generation of a module interrupt for an interrupt bit, set the corresponding bit in the Inter-
rupt Mask Register.
Clearing interrupts: All bits of the Pending Interrupt Register are cleared when it is read or when the
Pending Interrupt Masked Register is read. Reading the Pending Interrupt Masked Register yields the
contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register.
Selected bits can be cleared by writing ones to the bits that shall be cleared to the Pending Interrupt
Clear Register.
Forcing interrupts: When the Pending Interrupt Register is written, the resulting value is the original
contents of the register logically OR-ed with the write data. This means that writing the register can
force (set) an interrupt bit, but never clear it.
Reading interrupt status: Reading the Pending Interrupt Status Register yields the same data as a read
of the Pending Interrupt Register, but without clearing the contents.
Reading interrupt status of unmasked bits: Reading the Pending Interrupt Masked Status Register
yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask
Register, but without clearing the contents.
The interrupt registers comprise the following:
• Pending Interrupt Masked Status Register [PIMSR] R
• Pending Interrupt Masked Register [PIMR] R
• Pending Interrupt Status Register [PISR] R
• Pending Interrupt Register [PIR] R/W
• Interrupt Mask Register [IMR] R/W
• Pending Interrupt Clear Register [PICR] W
6: CS CLTU stored
5: OV Input data overrun
4: RBF Output buffer full
3: CR CLTU ready/aborted
2: FAR FAR available
1: BLO Bit Lock changed
Table 219.Interrupt registers
3176543210
- CS OV RBF CR FAR BLO RFA

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English