GR712RC-UM, Jun 2017, Version 2.9 200 www.cobham.com/gaisler
GR712RC
[1] The global system reset caused by the SRST-bit in the GRR-register results in the following actions:
- Initiated by writing a ‘1”, gives ‘0’ on read-back when the reset was successful.
- No need to write a ‘0’ to remove the reset.
- Unconditionally, means no need to check/disable something in order for this reset-function to correctly execute.
- Could of course lead to data-corruption coming/going from/to the reset core.
- Resets the complete core (all logic, buffers & register values)
- Behaviour is similar to a power-up.
[2] The FAR register supports the CCSDS/ECSS standard frame lengths (1024 octets), requiring an 8 bit CAC field
instead of the 6 bits specified in
[PSS-04-151]. The two most significant bits of the CAC will thus spill over into
the "LEGAL/ILLEGAL" FRAME QUALIFIER field, Bit [26:25]. This is only the case when the PSS bit is set to '0'.
[3] Only inputs 0 trough 4 are implemented.
[4] The channel reset caused by the CRST-bit in the COR-register results in the following actions:
- Initiated by writing a ‘1”, gives ‘0’ on read-back when the reset was successful.
- No need to write a ‘0’ to remove the reset.
- All other bit’s in the COR are neglected (not looked at) when the CRST-bit is set during a write, meaning that
the value of these bits has no impact on the register-value after the reset.
- Unconditionally, means no need to check/disable something in order for this reset-function to correctly execute.
- Could of course lead to data-corruption coming/going from/to the reset channel.
- Resets the complete channel (all logic, buffers & register values)
- Except the ASR-register of that channel which remains it’s value.
- All read- and write-pointers are automatically re-initialized and point to the start of the ASR-address.
- All registers of the channel (except the ones described above) get their power-up value.
- This reset shall not cause any spurious interrupts.
[5] These bits are sticky bits which means that they remain present until the register is read and
that they are cleared automatically by reading the register.
[6] The value of the pointers depends on the content of the corresponding Address Space Register (ASR).
During a system reset, a channel reset or a change of the ASR register, the pointers are recalculated
based on the values in the ASR register.
The software has to take care (when programming the ASR register) that the pointers never have to cross a
16 MiB boundary (because this would cause an overflow of the 24-bit pointers).
It is not possible to write an out of range value to the RRP register. Such access will be ignored with an HERROR.
[7] An AMBA AHB ERROR response is generated if a write access is attempted to a register without any writeable bits.
[8] The channel reset caused by a write to the ASR-register results in the following actions:
- Initiated by writing an updated value into the ASR-register.
- Unconditionally, means no need to check/disable something in order for this reset-function to correctly execute.
- Could of course lead to data-corruption coming/going from/to the reset channel.
- Resets the complete channel (all logic & buffers) but not all register values, only the following:
- COR-register, TE & RE bits get their power-up value, other bits remain their value.
- STR-register, all bits get their power-up value
- Other registers remain their value
- Updates the ASR-register of that channel with the written value
- All read- and write-pointers are automatically re-initialized and point to the start of the ASR-address.
- This reset shall not cause any spurious interrupts
[9] During a channel reset the register is temporarily unavailable and HRETRY response is generated if accessed.
[10] It is not possible to write an out of range value to the RRP register. Such access will be ignored without an error.
[11] The PSS bit usage is supported.
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