GR712RC-UM, Jun 2017, Version 2.9 199 www.cobham.com/gaisler
GR712RC
Legend:
3: 1 RESERVED
Write: Don’t care.
Read: All zero.
0 CR (CLTU Ready) [5]
There is a worst case delay from the CR bit being asserted, until the data has actually been trans-
ferred from the receiver FIFO to the ring buffer. This depends on the bus load etc.
Write: Don’t care.
Read: ‘1’= new CLTU in ring buffer. ‘0’= no new CLTU in ring buffer.
Power-up default: 0x00000000
Table 216. Address Space Register (ASR)
[8]
31 10 9 8 7 0
BUFST RESERVED RXLEN
31: 10 BUFST (Buffer Start Address)
22-bit address pointer
This pointer contains the start address of the allocated buffer space for this channel.
Register has to be initialized by software before DMA capability can be enabled.
9: 8 RESERVED
Write: Don’t care.
Read: All zero.
7: 0 RXLEN (RX buffer length)
Number of 1kB-blocks reserved for the RX buffer.
(Min. 1 KiB = 0x00, Max. 256 KiB = 0xFF)
Power-up default: 0x00000000
Table 217. Receive Read Pointer Register (RRP)
[6] [9][10]
31 24 23 0
RxRd Ptr Upper RxRd Ptr Lower
31: 24 10-bit upper address pointer
Write: Don’t care.
Read: This pointer = ASR[31..24].
23: 0 24-bit lower address pointer.
This pointer contains the current RX read address. This register is to be incremented with the actual
amount of bytes read.
Power-up default: 0x00000000
Table 218. Receive Write Pointer Register (RWP)
[6] [9]
31 24 23 0
RxWr Ptr Upper RxWr Ptr Lower
31: 24 10-bit upper address pointer
Write: Don’t care.
Read: This pointer = ASR[31..24].
23: 0 24-bit lower address pointer.
This pointer contains the current RX write address. This register is incremented with the actual
amount of bytes written.
Power-up default: 0x00000000
Table 215. Status Register (STR)
[7]
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