COBHAM GR712RC - Page 198

GR712RC-UM, Jun 2017, Version 2.9 198 www.cobham.com/gaisler
GR712RC
7: 0
BLO (Bit Lock)
[3]
Only the implemented inputs 0 through 4 are taken into account. All other bits are zero.
Write: Don’t care.
Read: Bit[0] = input 0, Bit[7] = input 7
Power-up default: Depends on inputs.
Table 214. Control Register (COR)
31 24 23 10 9 8 1 0
SEB RESERVED CRST RESERVED RE
31: 24 SEB (Security Byte):
Write: ‘0x55’= the write will have effect (the register will be updated). 
Any other value= the write will have no effect on the register.
Read: All zero.
23: 10 RESERVED
Write: Don’t care.
Read: All zero.
9
CRST (Channel reset)
[4]
Write: ‘1’= initiate channel reset,‘0’= do nothing
Read: ‘1’= unsuccessful reset, ‘0’= successful reset
8: 1 RESERVED
Write: Don’t care.
Read: All zero.
0 RE (Receiver Enable) TCACT[4:0] inputs of the receiver are masked when the RE bit is disabled.
Read/Write: ‘0’= disabled, ‘1’= enabled
Power-up default: 0x00000000
Table 215. Status Register (STR)
[7]
31 11109 876 543 10
RESERVED RBF RESERVED RFF RESERVED OV RESERVED CR
31: 11 RESERVED
Write: Don’t care.
Read: All zero.
10 RBF (RX BUFFER Full)
Write: Don’t care.
Read: ‘0’ = Buffer not full,
‘1’= Buffer full (this bit is set if the buffer has less then 1/8 of free space)
9: 8 RESERVED
Write: Don’t care.
Read: All zero.
7 RFF (RX FIFO Full)
Write: Don’t care.
Read: ‘0’ = FIFO not full, ‘1’ = FIFO full
6: 5 RESERVED
Write: Don’t care.
Read: All zero.
4
OV (Overrun)
[5]
Write: Don’t care.
Read: ‘0’= nominal, ‘1’= data lost
Table 213. Physical Interface Register (PHIR)
[7]