GR712RC-UM, Jun 2017, Version 2.9 143 www.cobham.com/gaisler
GR712RC
18.5.4 Status register
The status register is read only and reflects the current status of the core.
Receive buffer status is cleared when there are no more messages in the fifo. The data overrun status
signals that a message which was accepted could not be placed in the fifo because not enough space
left. NOTE: This bit differs from the SJA1000 behavior and is set first when the fifo has been read
out.
When the transmit buffer status is high the transmit buffer is available to be written into by the CPU.
During an on-going transmission the buffer is locked and this bit is 0.
The transmission complete bit is set to 0 when a transmission request or self reception request has
been issued and will not be set to 1 again until a message has successfully been transmitted.
18.5.5 Interrupt register
The interrupt register signals to CPU what caused the interrupt. The interrupt bits are only set if the
corresponding interrupt enable bit is set in the interrupt enable register.
This register is reset on read with the exception of IR.0 which is reset when the fifo has been emptied.
Table 130.Bit interpretation of command register (SR) (address 2)
Bit Name Description
SR.7 Bus status 1 when the core is in bus-off and not involved in bus activities
SR.6 Error status At least one of the error counters have reached or exceeded the error warning
limit.
SR.5 Transmit status 1 when transmitting a message
SR.4 Receive status 1 when receiving a message
SR.3 Transmission complete 1 indicates the last message was successfully transferred.
SR.2 Transmit buffer status 1 means CPU can write into the transmit buffer
SR.1 Data overrun status 1 if a message was lost because no space in fifo.
SR.0 Receive buffer status 1 if messages available in the receive fifo.
Table 131.Bit interpretation of interrupt register (IR) (address 3)
Bit Name Description
IR.7 Bus error interrupt Set if an error on the bus has been detected
IR.6 Arbitration lost interrupt Set when the core has lost arbitration
IR.5 Error passive interrupt Set when the core goes between error active and error passive
IR.4 - not used (wake-up interrupt of SJA1000)
IR.3 Data overrun interrupt Set when data overrun status bit is set
IR.2 Error warning interrupt Set on every change of the error status or bus status
IR.1 Transmit interrupt Set when the transmit buffer is released
IR.0 Receive interrupt Set while the fifo is not empty.
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