GR740-UM-DS, Nov 2017, Version 1.7 82 www.cobham.com/gaisler
GR740
8 High-performance IEEE-754 Floating-point Unit
8.1 Overview
GRFPU is a high-performance FPU implementing floating-point operations as defined in the IEEE
Standard for Binary Floating-Point Arithmetic (IEEE-754) and the SPARC V8 standard (IEEE-1754).
Supported formats are single and double precision floating-point numbers. The advanced design com-
bines two execution units, a fully pipelined unit for execution of the most common FP operations and
a non-blocking unit for execution of divide and square-root operations.
The logical view of the GRFPU is shown in figure 7.
Figure 7. GRFPU Logical View
8.2 Functional description
8.2.1 Floating-point number formats
GRFPU handles floating-point numbers in single or double precision format as defined in the IEEE-
754 standard with exception for denormalized numbers. See section 8.2.5 for more information on
denormalized numbers.
8.2.2 FP operations
GRFPU supports four types of floating-point operations: arithmetic, compare, convert and move. The
operations implement all FP instructions specified by SPARC V8 instruction set, and most of the
operations defined in IEEE-754. All operations are summarized in table 62.
operand1
opid
opcode
operand2
start
9
6
64
64
round
flushid
2
6
flush
result
resid
allow
except
ready
3
6
64
6
cc
2
nonstd
Pipelined execution
unit
Iteration unit
GRFPU
clk
reset
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