GR740-UM-DS, Nov 2017, Version 1.7 212 www.cobham.com/gaisler
GR740
In order to allow several EDCL enabled GRETH controllers on the same sub-net without the need for
configuring the cores, the four least significant bits of the IP and MAC addresses are set via general
purpose I/O lines at reset. See the description of bootstrap signals in section 3.1. Note that the four
least significant bits of the IP and MAC addresses also will be reset if the Ethernet controllers are
reset via the clock gating unit.
14.6.4 EDCL buffer size
The EDCL has a dedicated internal 2 KiB buffer memory which stores the received packets during
processing. Table 233 shows how many concurrent packets the EDCL can handle, the maximum size
of each packet including headers and the maximum size of the data payload. Sending more packets
before receiving a reply than specified for the selected buffer size will lead to dropped packets. The
behavior is unspecified if sending packets exceeding the maximum allowed size.
14.7 Media Independent Interfaces
There are several interfaces defined between the MAC sublayer and the Physical layer. The
GRETH_GBIT supports the Media Independent Interface (MII) and the Gigabit Media Independent
Interface (GMII).
The GMII is used in 1000 Mbit mode and the MII in 10 and 100 Mbit. These interfaces are defined
separately in the 802.3-2002 standard but in practice they share most of the signals. The GMII has 9
additional signals compared to the MII. Four data signals are added to the receiver and transmitter
data interfaces respectively and a new transmit clock for the gigabit mode is also introduced.
Table 233.EDCL buffer size limitations
Total buffer size (KiB) Number of packet buffers Packet buffer size (B) Maximum data payload (B)
2 4 512 456
Table 234.Signals in GMII and MII.
MII and GMII GMII Only
txd[3:0] txd[7:4]
tx_en rxd[7:4]
tx_er gtx_clk
rx_col
rx_crs
rxd[3:0]
rx_clk
rx_er
rx_dv
To Next Page
Loading...
Need help?
General
