GR740-UM-DS, Nov 2017, Version 1.7 291 www.cobham.com/gaisler
GR740
19.7 Memory EDAC
19.7.1 BCH EDAC
The core provides BCH EDAC that can correct one error and detect two errors in a 32-bit word. For
each word, a 7-bit checksum is generated according to the equations below. A correctable error will be
handled transparently by the memory controller, but adding one waitstate to the access. If an un-cor-
rectable error (double-error) is detected, the current AHB cycle will end with an ERROR response
(see section 5.10 for information on ERROR response propagation). The EDAC can be used during
access to the PROM area by setting the PROM EDAC enable bit in the MCFG3 register. The equa-
tions below show how the EDAC checkbits are generated:
CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31
CB1
= D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28
CB2
= D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31
CB3
= D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29
CB4
= D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31
CB5
= D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
CB6
= D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
Data is always accessed as words (4 bytes at a time) and the corresponding checkbits are located at the
address acquired by inverting the word address (bits 2 to 27) and using it as a byte address. The same
chip-select is kept active. A word written as four bytes to addresses 0, 1, 2, 3 will have its checkbits at
address 0xFFFFFFF, addresses 4, 5, 6, 7 at 0xFFFFFFE and so on. All the bits up to the maximum
bank size will be inverted while the same chip-select is always asserted. This way all the bank sizes
can be supported and no memory will be unused (except for a maximum of 4 byte in the gap between
the data and checkbit area). A read access will automatically read the four data bytes individually
from the nominal addresses and the EDAC checkbit byte from the top part of the bank. Write accesses
must only be performed as individual byte accesses by the software, writing one byte at a time, and
the corresponding checkbit byte must be calculated and be written to the correct location by the soft-
ware
NOTE: when the EDAC is enabled in 8-bit bus mode, special precautions need to be taken to use
more than the first bank select (PROM_CEN[0]). See [FTMBCH] for further information.
19.7.2 EDAC Error reporting
As mentioned above an un-correctable error results in an AHB ERROR (see section 5.10 for informa-
tion on ERROR response propagation) response which can be monitored on the bus. Correctable
errors however are handled transparently and are not visible on the AHB bus. A sideband signal is
provided which is asserted during one clock cycle for each access for which a correctable error is
detected. This sideband signal is connected to the AHB status register monitoring the Slave I/O AHB
bus (see section 27).
Note that bit errors remain in external memory until a software-initiated re-write is performed at the
faulty memory location.
19.8 Bus Ready signalling
The PROMIO_BRDYN signal can be used to stretch all types of access cycles to the PROM and I/O
areas. The accesses will always have at least the pre-programmed number of waitstates as defined in
memory configuration registers 1 & 2, but will be further stretched until PROMIO_BRDYN is
asserted. PROMIO_BRDYN should be asserted in the cycle preceding the last one. If bit 29 in
MCFG1 is set, PROMIO_BRDYN can be asserted asynchronously with the system clock. In this
case, the read data must be kept stable until the de-assertion of PROMIO_OEN and PRO-
MIO_BRDYN must be asserted for at least 1.5 clock cycle. The use of PROMIO_BRDYN can be
enabled separately for the PROM and I/O areas. It is recommended that PROMIO_BRDYN is
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