GR740-UM-DS, Nov 2017, Version 1.7 292 www.cobham.com/gaisler
GR740
asserted until the corresponding chip select signal is de-asserted, to ensure that the access has been
properly completed and avoiding the system to stall.
Figure 33 shows the use of BRDYN with asynchronous sampling. BRDYN is kept asserted for more
than 1.5 clock-cycle. Two synchronization registers are used so it will take at least one additional
cycle from when BRDYN is first asserted until it is visible internally. In figure 33 one cycle is added
to the data2 phase.
Figure 32. READ cycle with one extra data2 cycle added with BRDYN (synchronous sampling). Lead-out cycle is only
applicable for I/O accesses.
data1 data2
promio_address
prom_cen/io_sn
promio_data
promio_oen
data2 lead-out
clk
D1
A1
promio_brdyn
Figure 33. BRDYN (asynchronous) sampling. Lead-out cycle is only applicable for I/O-accesses.
data1 data2
promio_addr
prom_cen/io_sn
promio_data
promio_oen
data2 lead-out
clk
D1
A1
promio_brdyn