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GR740
it's own timer and interrupt controller, and also so the processor can not write to the page tables
themselves.
• Code in each partition can now run separated.
Note that the supervisor code running on the processors have to be trusted/audited to not manipulate
the MMU setup in an illegal way (through stores to MMU configuration ASI 0x19) after it has been
setup.
The level-2 cache can be either shared between the partitions, or it can be partitioned to reduce timing
interference. This may be done by using the level-2 caches single master per way option. Another
more flexible option is using the MMU address translation inside each partition to map the virtual
address space to physical address ranges that can never end up in the same level-2 sets (only physical
addresses with the same address bits 18:5 can end up in the same L2 set, and the MMU translation
allows translation of bits 31:12).
5.6 Clock gating
Some peripherals are clock gated after reset (see section 4.9). Software drivers for LEON systems
generally assume that the peripheral clocks are enabled and the clock gating unit should be configured
by the bootloader or debug tool. The GRMON debugger has support for enabling all clocks when con-
necting to the device and clocks for specific peripherals can also be enabled via the command line
interface. Please see the GRMON user manual and operating system documentation for more infor-
mation.
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