GR740-UM-DS, Nov 2017, Version 1.7 78 www.cobham.com/gaisler
GR740
6.10.10 MMU fault status register
The MMU fault status register is located in ASI 0x19 offset 0x300, and the definition is based on the
SRMMU specification in the SPARC V8 manual. The SPARC V8 specifies that the fault status regis-
ter should be cleared on read, on the LEON4 only the FAV bit is cleared on read. The FAV bit is
always set on error in the LEON4 implementation, so it can be used as a valid bit for the other fields.
6.10.11 MMU fault address register
The MMU fault address register is located in ASI 0x19 offset 0x400, and the definition follows the
SRMMU specification in the SPARC V8 manual..
6.11 Software considerations
6.11.1 Register file initialization on power up
It is recommended that the boot code for the processor writes all registers in the IU and FPU register
files before launching the main application. This allows software to be portable to both FT and non-
FT versions of the LEON3 and LEON4 processors.
6.11.2 Start-up
After reset, the caches are disabled and the cache control register (CCR) is 0. Before the caches may
be enabled, a flush operation must be performed to initialized (clear) the tags and valid bits. A suitable
assembly sequence could be:
flush
set 0x81000f, %g1
sta %g1, [%g0] 2
Table 60. ASI 0x19, offset 0x300 - FSR - MMU Fault Status Register
31 18 17 10 9 8 7 5 4 2 1 0
RESERVED EBE L AT FT F
A
V
O
W
0000000
rrrrrrr
31: 18 RESERVED
17: 10 External bus error (EBE) - Never set on the LEON4
9: 8 Level (L) - Level of page table entry causing the fault
7: 5 Access type (AT) - See V8 standard
4: 2 Fault type (FT) - See table 40.
1 Fault address valid (FAV) - Cleared on read, always written to 1 on fault
0 Overwrite (W) - Multiple faults of the same priority encountered
Table 61. ASI 0x19, offset 0x400 - FAR - MMU Fault Address Register
31 12 11 0
RESERVED
NR 0
rr
31: 12 Fault Address (FAULT ADDRESS) - Top bits of virtual address causing translation fault
11: 0 RESERVED
To Next Page
Loading...
Need help?
General
