GR740-UM-DS, Nov 2017, Version 1.7 18 www.cobham.com/gaisler
GR740
2.2 Cores
The design is based on the following IP cores from the GRLIB IP Library:
The information in the last two columns is available via plug’n’play information in the system and is
used by software to detect units and to initialize software drivers.
Table 6. Used IP cores
Core Function
Documented in
section Vendor Device
AHB2AHB Uni-directional AHB/AHB bridge 32, 18 0x01 0x020
AHBJTAG JTAG/AHB Debug interface 34 0x01 0x01C
AHBSTAT AHB Status Register 27 0x01 0x052
AHBTRACE AHB trace buffer 36 0x01 0x017
APBCTRL AHB/APB bridge 38 0x01 0x006
IRQ(A)MP Multiprocessor interrupt controller 21 0x01 0x00D
APBUART 8-bit UART with FIFO 23 0x01 0x00C
DSU4 LEON4 Debug Support Unit 33 0x01 0x049
MMCTRL Memory controller 10 0x01 0x05D
GPTIMER Modular timer unit with watchdog 20 0x01 0x011
GR1553B MIL-STD-1553B / AS15531 interface 16 0x01 0x04D
GRCAN CAN 2.0 controller with DMA 17 0x01 0x03D
GRCLKGATE Clock gating unit 25 0x01 0x02C
GRETH_GBIT 10/100/1000 Ethernet MAC with DCL 14 0x01 0x01D
GRGPIO General Purpose I/O Port 22 0x01 0x01A
GRGPRBANK General Purpose Register Bank 30 0x01 0x08F
GRGPREG General Purpose Register 28 0x01 0x087
GRIOMMU AHB/AHB bridge with protection (IOMMU) 12 0x01 0x04F
GRPCI2 Fast 32-bit PCI bridge 15 0x01 0x07C
GRSPW2 SpaceWire codec with RMAP 35 0x01 0x029
GRSPWROUTER SpaceWire router switch 13 0x01 0x08B
GRSPWTDP SpaceWire - Time Distribution Protocol 31 0x01 0x097
FTMCTRL 8/16/32-bit memory controller with EDAC 19 0x01 0x054
L2CACHE Level 2 cache 9 0x01 0x04B
L4STAT LEON4 statistical unit 26 0x01 0x047
LEON4 LEON4 SPARC V8 32-bit processor 6 0x01 0x048
MEMSCRUB Memory scrubber 11 0x01 0x057
SPICTRL SPI controller 24 0x01 0x02D
GR740THSENS GR740 Temperature sensor controller 29 0x01 0x099
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