GR740-UM-DS, Nov 2017, Version 1.7 107 www.cobham.com/gaisler
GR740
10.6 Registers
The controller has a register area accessible via the AHB slave interface. The registers should be
accessed with 32-bit reads and writes. The registers are tabulated below.
Table 94. MMCTRL Registers
Offset Register
0x00 SDRAM configuration register 1(SDCFG1)
0x04 SDRAM configuration register 2 (SDCFG2)
0x08 - 0x1C Reserved
0x20 Mux Configuration Register (MUXCFG)
0x24 Mux Diagnostic Address register (FTDA)
0x28 FT Diagnostic Checkbit register (FTDC)
0x2C FT Diagnostic Data register (FTDD)
0x30 FT Code Boundary Register (FTBND)
0x34 - 0xFF Reserved
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