GR740-UM-DS, Nov 2017, Version 1.7 234 www.cobham.com/gaisler
GR740
15.10.1
Table 272.0x00 - CTRL - Control register
Control register
31 30 29 28 27 26 25 24 23 16 15 12 11 10 9 8 7 4 3 0
RE MR TR R SI PE ER EI Bus Number RESERVED D
F
A
IB CB DIF Device INT mask Host INT mask
00000000 0 0 0000 0 0
rw rw rw r rw rw rw rw rw r rw rw rw rw rw rw
31 PCI reset (RE) - When set, the PCI reset signal is asserted. Needs to be cleared to deassert PCI reset.
30 PCI master reset (MR) - Set to reset the cores PCI master. This bit is self clearing.
29 PCI target reset (TR) - Set to reset the cores PCI target. This bit is self clearing.
28 RESERVED
27 System error interrupt (SI) - When set, Interrupt is enabled for System error (SERR)
26 Parity error response (PE) - When set, AHB error response is enabled for Parity error
25 Abort error response (ER) - When set, AHB error response is enabled for Master and Target abort.
24 Error interrupt (EI) - When set, Interrupt is enabled for Master and Target abort and Parity error.
23: 16 Bus Number - When not zero, type 1 configuration cycles is generated.This field is also used as the
Bus Number in type 1 configuration cycles.
15: 12 RESERVED
11 Disable internal AHB-slave / DMA fair arbitration (DFA). When this bit is set, the arbitration is done
when the current transfer has complete.
10 IO burst enable (IB) - When set, burst accesses may be generated by the PCI master for PCI IO
cycles
9 Configuration burst enable (CB) - When set, burst accesses may be generated by the PCI master for
PCI configuration cycles.
8 Device interrupt force (DIF) - When set, a PCI interrupt is forced.
7: 4 Device interrupt mask - When bit[n] is set dirq[n] is unmasked
3: 0 Host interrupt mask -ï€
bit[3] = 1: unmask INTD.ï€
bit[2] = 1: unmask INTC.ï€
bit[1] = 1: unmask INTB.ï€
bit[0] = 1: unmask INTA.
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