COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 235 www.cobham.com/gaisler
GR740
15.10.2
Table 273.0x04 - STATCAP - Status and Capability register
Status and capability register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 12 11 8 7 5 4 2 1 0
H
o
s
t
M
S
T
T
A
R
D
M
A
DI HI IRQ
mode
T
r
a
c
e
RES C
F
G
D
O
C
F
G
E
R
Core interrupt status Host interrupt
status
RES FDEPTH FNUM
*
1111101000 0 *
0
32
rrrrrrrrrrr wc r r r r
31 System Host indicator (Host) - When zero, the core is inserted in the System slot and is allowed to
act as System Host.
30 Master implemented (MST)
29 Target implemented (TAR)
28 DMA implemented (DMA)
27 Device Interrupt (DI) - Device drives PCI INTA
26 Host Interrupt (HI) - Device samples PCI INTA..D (for host operations)
25: 24 APB IRQ mode
00: PCI INTA..D, Error interrupt and DMA interrupt on the same IRQ signal
01: PCI INTA..D and Error interrupt on the same IRQ signal. DMA interrupt on IRQ+1
10: PCI INTA..D on IRQ..IRQ+3. Error interrupt and DMA interrupt on IRQ.
11: PCI INTA..D on IRQ..IRQ+3. Error interrupt on IRQ. DMA interrupt on IRQ+4
23 PCI trace buffer implemented (Trace)
22: 21 RESERVED
20 PCI configuration access done (CFGDO) - PCI configuration error status valid.
19 PCI configuration error (CFGER) - Error during PCI configuration access
18: 12 Core Interrupt status:
bit[6]: PCI target access discarded due to time out (access not retried for 2
15
PCI clock cycles)
bit[5]: System error
bit[4]: DMA interrupt
bit[3]: DMA error
bit[2]: Master abort.
bit[1]: Target abort.
bit[0]: Parity error..
11: 8 Host interrupt status
bit[3] = 0: indicates that INTD is asserted.
bit[2] = 0: indicates that INTC is asserted.
bit[1] = 0: indicates that INTB is asserted.
bit[0] = 0: indicates that INTA is asserted.
7: 5 RESERVED
4: 2
FIFO depth (FDEPTH) - Words in each FIFO = 2
(FIFO depth)
1: 0 Number of FIFOs (FNUM)

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English