GR740-UM-DS, Nov 2017, Version 1.7 70 www.cobham.com/gaisler
GR740
6.10.2 ASR16, LEON4FT register file protection register
The ancillary state register 16 (%asr16) provides information on errors detected in the processor’s
register files.
Table 49. %asr16 - LEON4FT register file protection register
31 43210
RESERVED FPCE IUCE
000
rrwrw
31: 4 RESERVED
3: 2 FP register file correctable error (FPCE) - Flag set when a correctable error has been detected in the
FP register file. Bit 1 flags uneven registers and bit 0 flags even registers.
1: 0 IU register file correctable error (IUCE) - Flag set when a correctable error has been detected in the
IU register file. Bit 1 flags uneven registers and bit 0 flags even registers.
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