GR740-UM-DS, Nov 2017, Version 1.7 391 www.cobham.com/gaisler
GR740
suspended when the processor enters debug mode, unless the trace force bit (TF) in the trace control
register is set. If the trace force bit is set, the trace buffer is activated as long as the enable bit is set.
The force bit is reset if an AHB breakpoint is hit and can also be cleared by software. Note that neither
the trace buffer memory nor the breakpoint registers (see below) can be read/written by software
when the trace buffer is enabled.
The DSU has an internal time tag counter and this counter is frozen when the processor enters debug
mode. When AHB tracing is performed in debug mode (using the trace force bit) it may be desirable
to also enable the time tag counter. This can be done using the timer enable bit (TE). Note that the
time tag is also used for the instruction trace buffer and the timer enable bit should only be set when
using the DSU as an AHB trace buffer only, and not when performing profiling or software debug-
ging. The timer enable bit is reset on the same events as the trace force bit.
The AHB trace buffer is enabled after reset when the DSU_EN signal is HIGH and the BREAK signal
is low.
33.3.1 AHB trace buffer filters
The DSU has filters that can be applied to the AHB trace buffer, breakpoints and watchpoints. These
filters are controlled via the AHB trace buffer filter control and AHB trace buffer filter mask registers.
The fields in these registers allows masking access characteristics such as master, slave, read, write
and address range so that accesses that correspond to the specified mask are not written into the trace
buffer. Address range masking is done using the second AHB breakpoint register set. The values of
the LD and ST fields of this register has no effect on filtering.
33.3.2 AHB statistics
The DSU collects statistics from the traced AHB bus and assert signals that are connected to the
LEON4 statistics unit (L4STAT). The statistics outputs can be filtered by the AHB trace buffer filters,
this is controlled by the Performance counter Filter bit (PF) in the AHB trace buffer filter control reg-
ister. The DSU can collect data for the events listed in table 520 below.
Table 520.AHB events
Event Description Note
idle HTRANS=IDLE Active when HTRANS IDLE is driven on the AHB slave inputs and
slave has asserted HREADY.
busy HTRANS=BUSY Active when HTRANS BUSY is driven on the AHB slave inputs and
slave has asserted HREADY.
nseq HTRANS=NONSEQ Active when HTRANS NONSEQ is driven on the AHB slave inputs
and slave has asserted HREADY.
seq HTRANS=SEQ Active when HTRANS SEQUENTIAL is driven on the AHB slave
inputs and slave has asserted HREADY.
read Read access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL,
slave has asserted HREADY and the HWRITE input is low.
write Write access Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL,
slave has asserted HREADY and the HWRITE input is high.
hsize[5:0] Transfer size Active when HTRANS is SEQUENTIAL or NON-SEQUENTIAL,
slave has asserted HREADY.
ws Wait state Active when HREADY input to AHB slaves is low and AMBA
response is OKAY.
retry RETRY response Active when master receives RETRY response
split SPLIT response Active when master receives SPLIT response
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