COBHAM GR740 - Page 3

GR740-UM-DS, Nov 2017, Version 1.7 3 www.cobham.com/gaisler
GR740
6 LEON4 - Fault-tolerant High-performance SPARC V8 32-bit Processor ............................. 48
6.1 Overview ............................................................................................................................................... 48
6.2 LEON4 integer unit ............................................................................................................................... 50
6.3 Cache system......................................................................................................................................... 56
6.4 Memory management unit..................................................................................................................... 59
6.5 Floating-point unit................................................................................................................................. 60
6.6 Co-processor interface........................................................................................................................... 61
6.7 AMBA interface .................................................................................................................................... 61
6.8 Multi-processor system support ............................................................................................................ 63
6.9 ASI assignments .................................................................................................................................... 64
6.10 Configuration registers .......................................................................................................................... 69
6.11 Software considerations ........................................................................................................................ 78
7 Floating-point Control Unit ................................................................................................... 80
7.1 Floating-Point register file..................................................................................................................... 80
7.2 Floating-Point State Register (FSR)...................................................................................................... 80
7.3 Floating-Point Exceptions and Floating-Point Deferred-Queue ........................................................... 80
8 High-performance IEEE-754 Floating-point Unit ................................................................. 82
8.1 Overview ............................................................................................................................................... 82
8.2 Functional description ........................................................................................................................... 82
9 Level 2 Cache controller........................................................................................................ 86
9.1 Overview ............................................................................................................................................... 86
9.2 Operation ............................................................................................................................................... 86
9.3 Operation ............................................................................................................................................... 89
9.4 Registers ................................................................................................................................................ 92
10 SDRAM Memory Controller with Reed-Solomon EDAC .................................................. 100
10.1 Overview ............................................................................................................................................. 100
10.2 Operation ............................................................................................................................................. 100
10.3 Limitations........................................................................................................................................... 100
10.4 SDRAM back-end operation ............................................................................................................... 101
10.5 Fault-tolerant operation ....................................................................................................................... 104
10.6 Registers .............................................................................................................................................. 107
11 Memory Scrubber and AHB Status Register ....................................................................... 112
11.1 Overview ............................................................................................................................................. 112
11.2 Operation ............................................................................................................................................. 112
11.3 Registers .............................................................................................................................................. 115
12 IOMMU - Bridge connecting Master I/O AHB bus ............................................................ 121
12.1 Overview ............................................................................................................................................. 121
12.2 Bridge operation .................................................................................................................................. 121
12.3 General access protection and address translation .............................................................................. 124
12.4 Access Protection Vector..................................................................................................................... 125
12.5 IO Memory Management Unit (IOMMU) functionality..................................................................... 127
12.6 Fault-tolerance..................................................................................................................................... 130
12.7 Statistics............................................................................................................................................... 131
12.8 ASMP support ..................................................................................................................................... 131
12.9 Registers .............................................................................................................................................. 132
13 SpaceWire router.................................................................................................................. 142
13.1 Overview ............................................................................................................................................. 142