GR712RC-QSG
November 2018, Version 1.0
6 www.cobham.com/gaisler
Cfg. description I/O enabled
Jumper
position
Instrument Controller, type B UART0, UART1, UART2, UART3, UART4, UART5
SpaceWire-0, SpaceWire-1, SpaceWire-2, SpaceWire-3
SDRAM with optional Reed-Solomon
Ethernet
SPI
I2C
F
Once the board's jumpers are properly connected, the internal switch matrix must be driven by a set of enabling
conditions. It is important to note that to obtain a proper functioning system, the I/O interfaces of the required
configurations have to be enabled or clock ungated by software. See Chapter 2 and Table 9 of [RD-2] for further
details on the switch matrix.
The I/O matrix is not limited to these pre-defined configurations. Jumpers can be custom configured according to
the user requirements. See Section 2.4 of [RD-1] for further details.
2.4. UART
Jumpers JP1 and JP2 are used to select the output standard of the UART0 and UART1 interfaces between RS232
and RS422, and to route the signals to the J1 and J16 connectors respectively. In the default configuration the
interfaces are connected to the J1 connectors UART-0 and UART-1 using the RS232 standard. While UART0 is
not affected by the internal switch matrix, UART1 Rx is multiplexed and JP3 must be set to 3-4 in order to use
it. Refer to the GR712RC Development Board Schematic for more information on how to configure UART0 and
UART1 to use the RS422 standard.
2.5. PROM
The PROM width and PROM EDAC conditions are set by the state of the GPIO[3] and GPIO[1] pins at power up
of the Processor. These pins are provided with pull-down resistors to set the default mode to 8 bit with no EDAC.
If EDAC operation of the Flash PROM is desired, then jumper JP85 should be installed, to pull-up GPIO[1].
To Next Page
Loading...
Need help?
General
