Compaq Deskpro EP 6233 - Page 6

Technical Reference Guide
Compaq Deskpro EP Series Personal Computers
First Edition - April 1998
iv
3.3.1 PENTIUM II PROCESSOR.......................................................................................... 3-10
3.3.2 SYSTEM MEMORY.................................................................................................... 3-12
3.3.3 SUBSYSTEM CONFIGURATION............................................................................... 3-13
CHAPTER 4 SYSTEM SUPPORT.........................................................................................................
4.1 INTRODUCTION.................................................................................................................. 4-1
4.2 PCI BUS OVERVIEW...........................................................................................................4-2
4.2.1 PCI CONNECTOR.........................................................................................................4-3
4.2.2 PCI BUS MASTER ARBITRATION.............................................................................. 4-4
4.2.3 PCI BUS TRANSACTIONS...........................................................................................4-5
4.2.4 OPTION ROM MAPPING ............................................................................................. 4-8
4.2.5 PCI INTERRUPT MAPPING......................................................................................... 4-9
4.2.6 PCI POWER MANAGEMENT SUPPORT.....................................................................4-9
4.2.7 PCI CONFIGURATION............................................................................................... 4-10
4.3 AGP BUS OVERVIEW ....................................................................................................... 4-11
4.3.1 BUS TRANSACTIONS................................................................................................ 4-11
4.3.2 AGP CONFIGURATION ............................................................................................. 4-14
4.3.3 AGP CONNECTOR..................................................................................................... 4-15
4.4 ISA BUS OVERVIEW......................................................................................................... 4-16
4.4.1 ISA CONNECTOR ......................................................................................................4-17
4.4.2 ISA BUS TRANSACTIONS......................................................................................... 4-18
4.4.3 DIRECT MEMORY ACCESS......................................................................................4-20
4.4.4 INTERRUPTS.............................................................................................................. 4-23
4.4.5 INTERVAL TIMER..................................................................................................... 4-27
4.4.6 ISA CONFIGURATION............................................................................................... 4-27
4.5 SYSTEM CLOCK DISTRIBUTION.................................................................................... 4-28
4.6 REAL-TIME CLOCK AND CONFIGURATION MEMORY............................................... 4-29
4.6.1 CONFIGURATION MEMORY BYTE DEFINITIONS ................................................ 4-30
4.7 I/O MAP AND REGISTER ACCESSING............................................................................ 4-46
4.7.1 SYSTEM I/O MAP ...................................................................................................... 4-46
4.7.2 82371 SOUTH BRIDGE GPIO CONFIGURATION..................................................... 4-47
4.7.3 87309 I/O CONTROLLER CONFIGURATION ........................................................... 4-49
4.8 SYSTEM MANAGEMENT SUPPORT ............................................................................... 4-50
4.8.1 FLASH ROM WRITE PROTECT ................................................................................ 4-50
4.8.2 USER SECURITY........................................................................................................ 4-50
4.8.3 I/O SECURITY............................................................................................................ 4-51
4.8.4 POWER MANAGEMENT........................................................................................... 4-51
CHAPTER 5 INPUT/OUTPUT INTERFACES.....................................................................................
5.1 INTRODUCTION.................................................................................................................. 5-1
5.2 ENHANCED IDE INTERFACE............................................................................................ 5-1
5.2.1 IDE PROGRAMMING................................................................................................... 5-1
5.2.2 IDE CONNECTOR........................................................................................................ 5-9
5.3 DISKETTE DRIVE INTERFACE........................................................................................5-10
5.3.1 DISKETTE DRIVE PROGRAMMING ........................................................................ 5-11
5.3.2 DISKETTE DRIVE CONNECTOR.............................................................................. 5-14
5.4 SERIAL INTERFACE......................................................................................................... 5-15