Compaq Deskpro EP 6233 - Table of Contents

Technical Reference Guide
Compaq Deskpro EP Series Personal Computers
First Edition – April 1998
iii
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION.............................................................................................................
1.1 ABOUT THIS GUIDE ........................................................................................................... 1-1
1.1.1 USING THIS GUIDE.....................................................................................................1-1
1.1.2 ADDITIONAL INFORMATION SOURCES.................................................................. 1-1
1.2 NOTATIONAL CONVENTIONS.......................................................................................... 1-2
1.2.1 VALUES........................................................................................................................ 1-2
1.2.2 RANGES........................................................................................................................ 1-2
1.2.3 SIGNAL LABELS..........................................................................................................1-2
1.2.4 REGISTER NOTATION AND USAGE ......................................................................... 1-2
1.2.5 BIT NOTATION............................................................................................................ 1-2
1.3 COMMON ACRONYMS AND ABBREVIATIONS.............................................................. 1-3
CHAPTER 2 SYSTEM OVERVIEW.....................................................................................................
2.1 INTRODUCTION.................................................................................................................. 2-1
2.2 FEATURES...........................................................................................................................2-2
2.2.1 STANDARD FEATURES..............................................................................................2-2
2.2.2 OPTIONS.......................................................................................................................2-2
2.3 MECHANICAL DESIGN...................................................................................................... 2-3
2.3.1 CABINET LAYOUT......................................................................................................2-3
2.3.2 CHASSIS LAYOUT....................................................................................................... 2-4
2.3.3 SYSTEM BOARD LAYOUT ......................................................................................... 2-5
2.4 SYSTEM ARCHITECTURE..................................................................................................2-6
2.4.1 PROCESSOR.................................................................................................................2-8
2.4.2 MEMORY...................................................................................................................... 2-8
2.4.3 SUPPORT CHIPSET...................................................................................................... 2-9
2.4.4 MASS STORAGE.......................................................................................................... 2-9
2.4.5 SERIAL AND PARALLEL INTERFACES .................................................................... 2-9
2.4.6 UNIVERSAL SERIAL BUS INTERFACE...................................................................2-10
2.4.7 GRAPHICS SUBSYSTEM........................................................................................... 2-10
2.5 SPECIFICATIONS.............................................................................................................. 2-11
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM........................................................................
3.1 INTRODUCTION.................................................................................................................. 3-1
3.2 66-MH
Z
SLOT 1 PROCESSOR/MEMORY SUBSYSTEM ................................................... 3-2
3.2.1 CELERON PROCESSOR............................................................................................... 3-3
3.2.2 PENTIUM II PROCESSOR............................................................................................ 3-3
3.2.3 PROCESSOR CHANGING/UPGRADING..................................................................... 3-4
3.2.4 SYSTEM MEMORY...................................................................................................... 3-5
3.2.5 SUBSYSTEM CONFIGURATION.................................................................................3-8
3.3 100-MH
Z
SLOT 1 PROCESSOR/MEMORY SUBSYSTEM..................................................3-9