Chapter 4 System Support
Compaq Deskpro Personal Computers
Third Edition – April 2001
4-2
4.2 PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation
in this particular system. For detailed information regarding PCI bus operation, refer to
the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the GMCH and ICH2 are organized as
multiple devices). A function is defined as the end source or target of the bus transaction. A device
may contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the 815E chipset components and is not physically accessible. The AGP
bus that services the AGP slot (or resident AGP controller on the Small Form Factor) is designated
as PCI bus #1. All PCI slots and the NIC function internal to the 82801BA reside on PCI bus #2.
Figure 4-1. PCI Bus Devices and Functions
Hub Link Bus
82815 GMCH Component
AGP 
Bridge 
Function
Mem. Cntlr. 
Function
PCI 
Bus #0
Slim Desktop and Configurable Minitower models only. 
82801BA ICH2 Component
PCI Bridge 
Function
NIC 
I/F 
Function
EIDE 
Controller 
Function
USB 
I/F 
Function
SMBus 
Controller 
Function
LPC 
Bridge 
Function
AC97 
Audio 
Function
PCI Bus #0
AGP Connector 
PCI Bus #1 
(AGP Bus)
Hub Link I/F
PCI  
Bus #2
PCI  
Bus #2
PCI Connector 1
PCI Connector 2
PCI Connector 5
PCI Connector 3
PCI Connector 4
Hub Link I/F