CP-850FX Service Manual
Europe R&D
23
z 2D and 3D frames for master and slave channel
z Vertical chrominance shift for improved VCR picture quality
z Contrast, brightness and saturation control
- Sharpness improvement
z Digital color transition improvement (DCTI)
z Adaptive horizontal and vertical peaking (luminance)
z Digital luminance transition improvement (DLTI)
z Digital contrast improvement (DCI, master channel only)
- Three D/A converters
- 9 bit amplitude resolution for YUV, RGB output
- (Nominal) 72 MHz clock frequency with two-fold oversampling
- I2C bus control (400 kHz)
- 1.8 V± 5% and 3.3 V ± 5% supply voltages
- PMQFP80-1 or PMQFP144-1 packages
- Only one crystal necessary for whole IC and all color standards
4.2.3 PINNING
Pin Name I/O Description
1 VDDDACY S DAC(Y)
2 AYOUT O Y output
3 VSSDACY S DAC(Y)
4 VSSD2 S Supply voltage for digital (0V digital)
5 VDDD2 S Supply voltage for digital(1.8V digital)
6 SDA I/O I2C-Bus data
7 TMS I Testmode select (Connected to vdd33)
8 656VIN/BLANK I/O Separate V input for 656 / BLANK output
9 656CLK I/O Digital input / output clock
10 656IO7 I/O Digital input / output (MSB)
11 VSSP2 S Supply voltage for digital (0 V pad)
12 VDDP2 S Supply voltage for digital (3.3 V pad)
13 SCL I I2C-Bus clk
14 V I Vertical pulse for RGB input
15 656IO6 I/O Digital input / output
16 656IO5 I/O Digital input / output
17 HOUT O Horizontal output
18 H50 O Hout 50 Hz
19 ADR / TDI I I2C address / test data in
20 V50 O Vout 50 Hz
21 656IO4 I/O Digital input / output
22 656IO3 I/O Digital input / output
23 VOUT O Vertical output
24 RESET I Reset input (Reset active low)
25 VDDP3 S Supply voltage for digital (3.3 V pad)
26 VSSP3 S Supply voltage for digital (0 V pad)
27 CLKOUT O Output clock (27 MHz nom.)
28 VDDD3 S Supply voltage for DRAM (1.8 V digital)
29 VSSD3 S Supply voltage for digital (0 V digital)
30 656IO2 I/O Digital input / output
31 656IO1 I/O Digital input / output
32 656IO0 I/O Digital input / output (LSB)
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