Denon AVR-2106 - Page 18

18
AVR-2106/886
TC94A27UG (IC201T,202T)
Function
Pin
No.
Pin Name I/O
* For latch-up countermeasure, perform each power supply ON/OFF in the same timing.
28 XOUT O X’tal osc. connecting output terminal
29 XIN I X’tal osc. connection, external clock input terminal (24.576MHz or 12.288MHz)
30 DVDD — Digital power
31 DGND — Digital GND
32 EMPHA/UO I/O Emphasis information/U-data output/Chip address setting terminal
33 AUDIO/VO I/O Non-PCM detect/V-flag output/ Chip address setting terminal
34 CKST I/O Clock switch transition period output/Demodulation master or slave function switching terminal
35 INT I/O Interrupt output for µcom (Interrupt factor selectable)/Modulation or general I/O switching terminal
36 RERR O PLL lock error, data error flag output
37 DO O µcom I/F, read out data output terminal (3-state)
38 DI I µcom I/F, write data input terminal
39 CE I µcom I/F, chip enable input terminal
40 CL I µcom I/F, clock input terminal
41 XMODE I System reset input terminal
42 DGND — Digital GND
43 DVDD — Digital power
44 TMCK/PIO0 I/O 256fs system clock input for modulation/General I/O in/output terminal
45 TBCK/PIO1 I/O 64fs bit clock input for modulation/General I/O in/output terminal
46 TLRCK/PIO2 I/O fs clock input for modulation/General I/O in/output terminal
47 TDATA/PIO3 I/O Serial audio data input for modulation/General I/O in/output terminal
48 TXO/PIOEN O/I Modulation data output/ General I/O enable input terminal
NC
L‑TVR‑REFB
L‑TVR‑1NB
L‑MVR‑1NB
L‑MVR‑OUTB
L‑TVR‑OUTB
L‑MVR‑AGNDB2
L‑MVR‑AGNDARE
L‑MVR‑AGNDARE
L‑MVR‑AGNDA2
NC
L‑MVR‑AGNDB1
NC
12
1110
9
87654321
13
14
15
16
17
19
18
20
21
22
44
43
42
41
40
39
37
38
36
35
34
23
24
25
26
27
30
29
28
31
3233
R‑TVR‑REFB
R‑TVR‑1NB
R‑MVR‑1NB
R‑MVR‑OUTB
R‑TVR‑OUTB
R‑MVR‑AGNDB2
R‑MVR‑AGNDA1
R‑MVR‑AGNDA2
R‑MVR‑OUTA
NC
R‑MVR‑AGNDB1
L‑MVR‑INA R‑MVR‑INA L‑TVR‑INA L‑TVR‑OUTA
L‑TVR‑REPA R‑TVR‑REF
R‑TVR‑INA
R‑TVR‑OUTA
NC
CS1
VDD
TEST
GND
MUTEM
CS2
CK
MUTE
VSS
STB
DATA
LatchLatch
Levelshiftcircuit
Test&
autoclearcircuit
Timing
generating
circuit
Latch
Latch
LatchLatch Latch
Latch
Latch Latch
Latch
Decodercircuit
24bitshiftregister
Decodercircuit
Latch
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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