Denon AVR-2106 - Page 19

19
AVR-2106/886
AS7C34096A-10TCN (IC806,817)
TC90A69F (IC1009) NJM2274R (IC1007)
LC75721 (IC301) BU2090 (IC302,1003,1005)
14 15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
11
A
13
A
12
A
CE
A A
16
A
17
A
9
A
18
A
10
Top View
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
WE
V
CC
V
SS
A
18
A
15
A
12
A
14
I/O
5
I/O
4
A
9
A
0
I/O
0
I/O
1
I/O
2
I/O
3
OE
A
17
A
16
A
13
CE
NC
NC
NC
NC
I/O
7
I/O
6
V
CC
V
SS
A
10
A
11
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
37
40
39
38
41
44
43
42
9
10
11
14
31
32
36
35
34
33
12
13
16
15
29
30
18
19
20
21
22
17
27
26
25
24
23
28
POWER
1
2
3
4
5
7
8
6
TOP
VIEW
1Yin
Cin
7
C Mute CTL
2
GND
Disc.
Vref
7
Power Save CTL
2
Vcc
Clamp
8 Bias
+
+
Vsag4
3 Vout
750
ohm
1
BIAS VB1
2
VRT
27
COUT
3
VDD1
26
VSS1
4
TESTI1
25
YOUT
5
VSS2
24
VB2
6
VRB
23
PD
7
YCIN
22
FIL
8
TEST
21
VSS4
9
KILLER
20
VDD4
10
TESTI2
19
FSC
11
VDD3
18
TESTOUT
12
VSS3
17
MODE1
13
VDD2
16
SDA
14
TESTI3
15
SCL
CORING
PEAKING
DAC
1/8
(8fsc)
8fsc 4fsc
DAC
IIC BUS
28
PLL DET 1/2VCO
Ped.
CLIP
LPF
DELAY
CNR
C-N.C
CORING V-ENHANCER
KILLER
DYNAMIC COMB FILTER
Sync. Clamp
ADC
LINE
MEMORY
LINE
MEMORY
INTERPOLATION
64
49
48 33
32
17
161
AM 1 AM 2 AM 3 AM 4 AM 5 AM 6 AM 7 AM 8 AM 9 AM 10 AM 11 AM 12 AM 13 AM 14 AM 15 AM 16
AM 17
AM 18
AM 19
AM 20
AM 21
AM 22
AM 23
AM 24
AM 25
AM 26
AM 27
AM 28
AM 29
AM 30
AM 31
AM 32
G7 G8 G9 G10 G11 AA8/G12 AA7/G13 AA6/G14 AA5/G15 AA4/G16 AA3 AA2 AA1 AM35 AM34 AM33
DI
CL
CE
RES
V
DD
OSCI
OSCO
Vss
TEST
V
FL
G1
G2
G3
G4
G5
G6
Symbol
V
DD
Vss
Power terminal +5V
Power terminal GND
V
FL
Power terminal FL drive
DI
CL
CE
Serial data transfer terminal
DI: Data
CL: Clock
CE: Chip enable
OSCI
OSCO
External CR connecting terminal
RES
System reset terminal
AM1~AM35
AA1~AA3
Anode output terminal
AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12
Anode/Grid output terminal
G1~G11 Grid output terminal
TEST LSI test terminal
Function
LC75721E Terminal Function
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11Q3
VDD
OE
Q7
Q8
Q11
Q10
Q9
Q6
VSS
DATA
CLOCK
LCK
Q0
Q1
Q2
9
10
Q4
Q5
CONTROL CIRCUIT
12-bit SHIFT REGISTER
12-bi t STRAGE REGI STER
OUTPUT BUFFER ( OPEN DRA I N)
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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