23
AVR-5803/AVC-A1SR
23
32 P64/CTS1 REQ O C ——Eu Z L
Main/Sub-mcom comm. control output (RTS from sub-mcom L)
33 P63/TXD0 MISO O C ——— Z L Main/Sub-mcom comm. control terminal (Data output)
34 P62/RXD0 MOSI I — Lv —— Z L Main/Sub-mcom comm. control terminal (Data input)
35 P61/CLK0 CLK I/O C ——— ZL
Main/Sub-mcom comm. control terminal (I2C clock in/output)
36 P60/CTS0 DACMDO I — Lv —— Z — DAC control terminal (PCM1738)
37 P57 DACMDI O C ——— Z L DAC control terminal (PCM1738)
38 P56 DLINK ON O C ——— Z L DENON LINK ON terminal (H: DENON LINK)
39 P55/EPM FRASH EPM I — Lv —— Z — When rewrite boot program on, L input set
40 P54 _INT3 I — Lv —— Z — DIR3 control terminal (LC89057W-E)
41 P53 _INT4 I — Lv —— Z — DIR4 control terminal (LC89057W-E)
42 P52 PTMS I ———— Z — ASIC control terminal
43 P51 PTDO I — Lv —— Z — ASIC control terminal
44 P50/CE FRASH CE I ———— Z — When rewrite boot program on, H input set
45 P47 PTCK I ———— Z — ASIC control terminal
46 P46 PTDI I ———— Z — ASIC control terminal
47 P45 D. EXP OE O C ——— ZL
Port Expander control output for Digital input switching (BU4094B)
48 P44 D. EXP CLK O C ——— ZL
Port Expander control output for Digital input switching (BU4094B)
49 P43 D. EXP DATA O C ——— ZL
Port Expander control output for Digital input switching (BU4094B)
50 P42 D. EXP STB O C ——— ZL
Port Expander control output for Digital input switching (BU4094B)
51 P41 XTALRST O C ——— Z H Clock for DIR (L: Osc. stop)
52 P40 DSD SEL O C ——— Z L H: DSD
53 P37 iLink DE O C ——— Z L iLink control terminal
54 P36 iLink RE O C ——— Z H iLink control terminal
55 P35 iLink SEL O C ——— Z L iLink control terminal (H: 1394)
56 P34 DSP I/O POWER O C ——— Z L H: Power ON (On 10ms later from Digital Power On)
57 P33 DSP OSC ON O C ——— Z L H: ON (On 20ms later from Digital Power On)
58 P32 DSP2_RS O C ——— Z L DSP2 reset output (L: Reset)
59 P31 DSP1_RS O C ——— Z L DSP1 reset output (L: Reset)
60 VCC VCC ———————+3V
61 P30
FLAG 1A (DSP_ACK1)
I — Lv —— Z — DSP1 host I/F comm. response input (L: OK)
62 VSS VSS ———————GND
63 P27 FLAG 2A (BUSY1) I — Lv —— Z —
DSP operation check flag (ADSP21161L-A: FLAG 2A), L: Normal
64 P26
IRQ1_B1 (DSP_REQ1)
OC——— ZL
DSP1 (ADSP21161L-A: IRQ 1_), host I/F interrupt request output, L: REQ
65 P25 FLAG 0A (WRITE1) O C ——— Z L DSP1 comm. control terminal (H: Data write)
66 P24
IRQ1_B2 (DSP_REQ2)
OC——— ZL
DSP2 (ADSP21161L-A: IRQ 1_), host I/F interrupt request output, L: REQ
67 P23 FLAG 0B (WRITE2) O C ——— Z L DSP2 comm. control terminal (H: Data write)
68 P22
FLAG 1B (DSP_ACK2)
I — Lv —— Z — DSP2 host I/F comm. response input (L: OK)
69 P21 FLAG 2B (BUSY2) I — Lv —— Z —
DSP operation check flag (ADSP21161L-B: FLAG 2B), L: Normal
70 P20 FLAG 3A I — Lv —— Z — Special flag for ROM update (ADSP21161L-A: FLAG 3A)
71 P17/INT5 AC-3 RF DET. I —
E↓&L
—— Z — AC-3 RF signal check input (H: AC-3 RF data input)
72 P16/INT4 FLAG 3B I — Lv —— Z — Special flag for ROM update (ADSP21161L-A: FLAG 3B)
73 P15/INT3 u ERROR I —
E↑&L
—— Z — DIR control input terminal (LC89057W), H: ERR
74 P14/D12 u SELCK O C ——— Z L ADC/DIR data, clock switching control terminal (L: ADC)
75 P13/D11 u ERR MUTE O C ——— Z H Pop noise preventive mute control output
76 P12/D10
u BSE (AC3 MUTE)
OC——— ZH
Digital mute control output (L: AC-3 or DTS decode enable)
77 P11/D9 REQ SUB O C ——— Z L 1394 comm. control terminal
78 P10/D8 ACK SUB O C ——— Z L 1394 comm. control terminal
79 P07/D7 I/08 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D23)
80 P06/D6 I/07 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D22)
81 P05/D5 I/06 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D21)
82 P04/D4 I/05 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D20)
83 P03/D3 I/04 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D19)
84 P02/D2 I/03 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D18)
85 P01/D1 I/02 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D17)
86 P00/D0 I/01 I/O C ——— Z L DSP comm. terminal (ADSP21161N:D16)
87 P107/AN7 DAC-RESET1 O C ——— ZL
DAC control terminal (L: Power down mode, ↑: Reset, H: Normal)
88 P106/AN6 FGAIN O C ——— ZL
IV Amp Gain switching control output (L: Subwoofer enable)
89 P105/AN5 _INT2 I — Lv —— Z — DIR2 control terminal (LC89057W-E)
90 P104/AN4 FDACCS O C ——— Z H DAC control terminal (PCM1738:Fch chip select)
91 P103/AN3 CDACCS O C ——— Z H DAC control terminal (PCM1738:Cch DAC chip select)
92 P102/AN2 SDACCS O C ——— Z H DAC control terminal (PCM1738:Sch DAC chip select)
93 P101/AN1 SBDACCS O C ——— Z H DAC control terminal (PCM1738:SBch DAC chip select)
94 AVSS AVSS ———————AD GND
95 P100/AN0 SPIDS1 O C ——— Z H DSP1 serial control terminal (ADSP21161N)
96 VREF VREF ———————AD ref. +3V
97 AVCC AVCC ———————AD +3V
98 P97/SIN4 SPIMISO I — Lv —— Z — DSP serial control terminal (ADSP21161N)
99 P96/SOUT4 SPIMOSI O C ——— Z L DSP serial control terminal (ADSP21161N)
100 P95/CLK4 SPICLK O C ——— Z L DSP serial control terminal (ADSP21161N)
Function
Pin
No.
Pin Name
DetI/O Type Ext Int Res Init
Symbol
To Next Page
Loading...
