Denon DCD-3520 - CXD1125 Q IC Pinout and Block Diagram

CXA1082AS/1182S
x 3 tgs “x ¢ Ww i S eo eo ag
Ps 3 § 62223 § 8 a8 a Ry $32882 328
hag ieee 53) igi 9-2?
LOOP FILTER ;
Thea | PE SLEV REGULATOR frye) Vow Joona oon rescore eres nee ann
|
I2L DATA REGISTER INPUT SHIFT REGISTER
ADDRESS DECODER
OUTPUT
DECODER
‘
FSi-4
=
TGI-2
TMi-7
PSi-3
RACKING PHASE COMPENSATION i
FOCUS PHASE Aa
COMPENSATION
.
Eicfee es eeset Veeue ted oe tee :
7
&
'
)-2)43) 4-5) (8)—@) (0)—(1!) @)—_4){5) 4 22) €4) :
oo # 2 8 w SF 8 8 318 wh 5 8S 8&8 t +93 58 & 7
ay Foe rare mck & & fF F Be peas ana a eg .
t
i
CXD11250 e
LRCk
WOCK
Yoo
=
OAIG~
DAO!
APTL
APTR
“
CLV SERVO ;
FRAME SYNC
CONTROL
DETECTOR/
v
PROTECTOR/
INSERTER ~
INTERPOLATOR bd
REGISTER
VCO CIRCUIT
TIMING
GENERATOR
OEMODULATOR Y,
CPU , 5
INTERFACE
SUBCODE X'TAL CIRCU
OEMODULATOR TIMING ,
GENERATOR
E TRACKING
COUNTER SUBCODE ! d
oo RAM ADORESS =
GENERATOR
CRCF EXCK SUBQ SCOR SOCK OOTX. 0B01 ~ 0808 Voo
$850 SQEX GFS
31
LAR ie a