Denon DCD-3520 - IC Terminal Function Lists (Cont.); CXD1125 Q Terminal Function Table (Part 2)

Tees
i,
1/0
Terminal
Function
46
r
RAOS
oO
|
Address
output
of
external
RAM.
ADDROQ.
47
RA10
q
oO
i
Address
output
of
external
RAM.
ADDR10.
48;
RAIi
|
O
|
Address
output
of
external
RAM.
ADDR11.
49
RAWE
|:
oO
|
Write
enable
signal
output
for
external
RAM.
(Active
at
“’L’’.}
50
i
RACS
Oo
|
Chip
select
signal
output
for
external
RAM.
(Active
at
i
Be)
51
cam
|
oO
Dividing
output
of
X‘tal.
f
=
4.2336
MHz.
52
Vss
=
GND
(OV).
53
XTAI
]
{
r
X'tal
oscillation
circuit
input.
By
selecting
of
mode,
f
=
8.4672
MHz
or
16.9344
MHz.
54
XTAO
i"
oO
X’tal
oscillation
circuit
output.
By
selecting
of
mode,
f
=
8.4672
MHz
or
16.9344
MHz.
55
MD1
I
a
Mode
selection
input
1.
56
MD2
I
Mode
selection
input
2.
57
MD3
|
T
Mode
selection
input
3.
58
SLOB
|
Code
switching
input
for
audio
data
output.
At
“L”
for
2‘s
compliment
output;
at
“‘H”
for
offset
binary
L
|
output.
59
PSSL
I
Mode
switching
input
for
audio
data
output.
At
L'
for
serial
output;
at
H”
for
parallel
output.
60
APTR
Oo
Control
output
for
aperture
compensation.
In
“‘H"
for
R-ch.
61
APTL
e)
Control
output
for
aperture
compensation.
In
‘‘H”
for
L-ch.
as
ae
—+
A
Ai
PSSL
.
ie
fot
pe
Ech
Parallel
voice
data)
output.
63
DAOQ2
0
i
At
PSSL
=
“H”
for
DAQ2
output;
PSSL
=
“L”
for
C1
F2
output.
64
|
DAQ3
a
fe)
ane
PSSL
=
"“H”
for
DAO3
output;
PSSL
=
“L”
for
C2F1
output.
ae
tr
ee
:
a
65
DAO4
oO
At
PSSL
=
"'H"
for
DA04
output;
PSSL
=
"L"
for
C2F2
Output.
At
PSSL
=
“H"
for
DAO6
output;
PSSL
=
"L"”
for
C2PO
output.
At
PSSL
=
“H”
for
DAO?
output;
PSSL
=
“L"
for
RFCK
output.
At
PSSL
=
“‘H”
for
DAO8
output;
PSSL
=
"L””
for
WFCK
output.
[ra oye)
Olo]~
O;O/o0
PIi>i >
ellis
i} "
eo
70
DAOS
(@)
At
PSSL
=
“H"
for
DAO9
output;
PSSL
=
“L”
for
PLCK
output.
ie)
At
PSSL
=
‘'H”
for
DA10
output;
PSSL
=
“L”
for
UGES
output.
oO
At
PSSL
=
“H”
for
DA11
output;
PSSL
=
“L"
for
GTOP
output.
Voo
-
Power
supply
(+5V).
=.
_|
74
|
DA12
At
PSSL
=
“H"
for
DA12
output;
PSSL
=
“L"
for
RAOV
output.
|
At
PSSL
=
“‘H"
for
DA13
output;
PSSL
=
“L”
for
C4LR
output.
At
PSSL
=
“H”
for
DA14
output;
PSSL
=
“L”
for
C210
output.
At
PSSL
=
“‘H”
for
DA15
output;
PSSL
=
“L"
for
C210
output.
At
PSSL
=
“H"
for
DA16
(MSB
of
parallel
voice
data)
output.
I
Strobe
signal
output.
At
DF
ON,
176.4
kHz.
At
CXD1
1250
or
DF
OFF,
88.2
kHz.
q8e—
1
BATE
At
PSSL
=
“L”
for
DATA
output.
bs
as
eae
|
a
WOCK
LRCK
Note:
UGFS:
aa
Monitor
output
for
error
correction
state
what
C1
is
at
GTOP:
Z1F2:
decode.
22F1:
Monitor
output
for
error
correction
state
what
C2
is
at
RAOV:
22F2:
decode.
S2FL:
Correction
state
output.
Becomes
‘‘H’’
when
C2
system
C4LR:
in
which
presently
under
correction
is
unable
to
correct.
22PO:
C2
pointer
indication
output.
Synchronizes
with
audio
C210:
data
output.
C210:
3FCK:
Read
frame
clock
output.
7.35
kHz
of
X
‘tal
system.
VFCK:
Write
frame
clock
output.
7.35
kHz
when
locked
on
to
DATA:
X'tal
system.
‘LCK:
=
VCO/2
output.
When
locked
to
EFM
signal,
f
=
4.3218
MHz.
Strobe
signal
output.
At
DF
ON,
88.2
kHz.
At
CXD11250
or
OF
OFF,
44.1
kHz.
Output
of
unprotected
frame
sync
pattern.
Indication
output
of
frame
synchro
in
protected
condi-
tion.
Overflow
and
underflow
indication
Outputs
of
+4
frame
jitter
absorbing
RAM.
Strobe
signal.
At
DF
ON,
352.8
kHz.
At
CXD1125Q
or
DF
OFF,
176.4
kHz.
Reverse
output
of
C210.
Bit
clock
output.
At
DF
ON,
4.2336
MHz.
At
CXD11250
or
DF
OFF,
2.1168
MHz.
Serial
data
output
of
audio
signal.
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