Denon DCD-720AE - Page 86

86
TERMINAL
NAME PIN
SNOITPIRCSED O/I
CPVDD 1 - Charge pump power supply, 3.3V
CAPP 2 O Charge pump flying capacitor terminal for positive rail
CPGND 3 - Charge pump ground
CAPM 4 O Charge pump flying capacitor terminal for negative rail
VNEG 5 O Negative charge pump rail terminal for decoupling, -3.3V
OUTL 6 O Analog output from DAC left channel
OUTR 7 O Analog output from DAC right channel
AVDD 8 - Analog power supply, 3.3 V
AGND 9 - Analog ground
VCOM 10 O VCOM output by register setting of VCOM mode is optional, default setting is VREF mode
When VREF mode (default), this pin ties to GND
When VCOM mode, decupling capacitor to GND is required
MOSI 11 I Input data for SPI
(1)
MC 12 I Input clock for SPI
(1)
GPIO5 13 I/O General purpose digital input and output port
GPIO4 14 I/O General purpose digital input and output port
GPIO3 15 I/O General purpose digital input and output port
GPIO2 16 I/O General purpose digital input and output port
MODE1 17 I
MS
(MODE2)
18 I
Mode control selection pin
(1)
MODE1=Low, MODE2=Low : Hardwired mode
MODE1=Low, MODE2=High : I2C mode
MODE1=High : SPI mode, MODE2 pin changes MS pin which is chip select for SPI
GPIO6 19 I/O General purpose digital input and output port
SCK 20 I System clock input
(1)
BCK 21 I Audio data bit clock input
(1)
DIN 22 I Audio data input
(1)
LRCK 23 I Audio data word clock input
(1)
MISO
(GPIO1)
24 I/O Primary output data for SPI readback
Secondary general purpose digital input and output port controlled by register
XSMT 25 I Soft mute control
(1)
: Soft mute (Low) / soft un-mute (High)
LDOO 26 - Internal logic supply rail terminal for decoupling, 1.8V
DGND 27 - Digital ground
DVDD 28 - Digital power supply, 3.3V or 1.8V
(1) Failsafe LVCMOS Schmitt trigger input.