Denon DN-C615 - Page 11

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11
DN-C615
33 P33,A11,_KI3 A11 A/O - - Unfix - Address bus
34 AVDD AVDD - - - - - Analog power supply terminal
35 P34,A12,_KI4 A12 A/O - - Unfix - Address bus
36 P35,A13,_KI5 A13 A/O - - Unfix - Address bus
37 P36,A14,_KI6 A14 A/O - - Unfix - Address bus
38 P37,A15,_KI7 A15 A/O - - Unfix - Address bus
39 P40,A16 A16 A/O - - Unfix - Address bus
40 P41,A17 A17 A/O - - Unfix - Address bus
41 P42,A18 A18 A/O - - Unfix - Address bus
42 P43,A19 A19 A/O - - Unfix - Address bus
43 Vref- Vref- - - - - - Standard analog power supply
44 P44,AN4,A20 PPARA1 I Lv - Unfix - Parallel input 1 (Use A/D converter)
45 P45,AN5,A21 PPARA2 I Lv - Unfix - Parallel input 2 (Use A/D converter)
46 P46,AN6,STOP,
A22
PPARA3 I Lv - Hi-Z - Parallel input 3 (Use A/D converter)
47 P47,AN7,WDOUT,
A23
PSDA I/O - - Hi-Z - Not used.
48 P80,TM14OA PSCL O - - Hi-Z H Not used.
49 P81,TM14OB PDUB O - - Hi-Z H Dubbing signal 'L': Dubbing
50 P82,TM0IO,SBI2,
SBT3,SCL3
PMON1 I - - Hi-Z - Monitor signal 1
51 P83,TM4IO,SBI3 RxD I - - Hi-Z - Serial port (9600bps by xxMHz)
52 P84,TM7IO,SBO3,
SDA3
TxD O - - Hi-Z H Serial port (9600bps by xxMHz)
53 P85,TM9IOA,SBO2,
SBT4,SCL4
PFLCLK O - - Hi-Z H To FL driver SCK
54 Vref+ Vref+ - - - - - Standard analog power supply
55 P86,TM9IOB,SBI4 PFLCS O - - Hi-Z H To FL driver CS
56 P87,TM9IC,SBO4,
SDA4
PFLSD O - - Hi-Z H To FL driver SDATA
57 P90,TM8IOA,BIBT1,
_DMAREQ1
PBIAS O - Pd L L Bias signal 'H': BIAS ON
58 P91,TM10IOA,BIBT2,
_DMAACK1
PRMUTE O - Pu H H Rec mute change signal 'H': MUTE ON
59 P92,TM10IOB,
_DMAREQ0
PLRCK I Ed - Hi-Z - LRCK : Use for time code creation during MP3 playback.
60 P93,TM10IC,
_DMAACK0
PNRST O - Pd L L Round IC reset signal
61 Vss Vss - - - - - GND (0V)
62 P94,AN0 PADINL I Lv Pd L - Use A/D converter
63 P95,AN1 PADINR I Lv Pd L - Use A/D converter
64 P96,AN2 PREMO1 I Lv - Hi-Z - Use A/D converter
65 P97,AN3 PREMO2 I Lv - Hi-Z - Use A/D converter
66 Vdd Vdd - - - - - Power supply (+3.3V)
67 P70,SBT0,_RAS PMCLK O - - Hi-Z H DSP interface Clock (clock synchronous formula)
68 P71,SBI0,_CAS,
_LCAS
PSTAT I - - Hi-Z - DSP interface Reception (clock synchronous formula)
69 P72,SBO0,_UCAS PMDAT O - - Hi-Z H DSP interface Transmission (clock synchronous formula)
70 P73,SBT1,DUMX PTXTCLK O - - Hi-Z H Use during CD-TEXT data read (clock synchronous formula)
71 P74,SBI1 PTXTD I - - Hi-Z - Use during CD-TEXT data read (clock synchronous formula)
72 P75,SBO1 PMLD O - - Hi-Z H DSP interface latch
73 TEST1 TEST1 I - Pu - - Pull up 33 - 50K
74 TEST2 TEST2 I - Pu - - Pull up 33 - 50K
75 _NMI _NMI I Lv - Hi-Z - Need pull up
76 PA0,_IRQ0 PBLKCK I Ed - Hi-Z - Sub code clock interruption
77 PA1,_IRQ1 PDQSY I Ed - Hi-Z - CD-TEXT DQSY Interruption
78 PA2,_IRQ2 PPLS I Ed - Hi-Z - Count by DOWN EDGE. One rotation by three counts.
79 PA3,_IRQ3 PREMOTE I Ed - Hi-Z - RC-5/Infrared remote signal input
80 PA4,_IRQ4,TM15IB PCHGOFT O - Pu H L Off track signal
81 PA5,ADSEP ADSEP I - H H H 'H': Address data separation mode / 'L': Address data common mode
Pin
No.
Pin Name Symbol I/O Det Ext Res Ini Function