Denon DRA-F101 - Page 10

10
DRA-F101
TC74HC4066AF (IC104, 201)
LC75343M (IC106)
1I/O 1
14 V
CC
1O/I 2
13 1C
2O/I 3
12 4C
2I/O 4
11 4I/O
2C 5
10 4O/I
3C 6
9
GND 7
8
3O/I
3I/O
DI
CE
VSS
LOPOUT
LINM
LINP
LOUT
LSB
LBASS2
LBASS1
L
TRE
L
VRIN
LSEL0
L5
L4
L3
L2
L1
CL
VDD
R
OPOUT
RINM
RINP
R
OUT
RSB
RBASS2
RBASS1
R
TRE
R
VRIN
RSEL0
R5
R4
R3
R2
R1
Vref
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
93LC66 (IC905)
1
2
3
4
5
6
7
8
CS
SK
Vcc
DI
DO
WP
ORG
GND
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
DATA
REGISTER
ADDRESS
REGISTER
Vcc RANGE
DETECTOR
WRITE ENABLE
DUMMY BIT
R/W AMPS
HIGH VOLTAGE
GENERATOR
DECODER
MEMORY ARRAY
256/512 X 8
OR
64/128/256 X 16
DI
CS
SK
(2K/4K)
ORG
DO
BA15218F (IC202, 203)
NJM2068DDC (IC401)
NJM5532DD (IC309)
BA05T (IC907)
NJM7812FA(S) (IC101)
OUT
GND
IN
M51957BFP (IC903)
TOP VIEW
1
2
3
4
5
7
8
6
+
+
A
B
A OUT
A
−
IN
A+ IN
V+
B OUT
B
−
IN
B+ IN
V
−
1
2
3
4
5
7
8
6
NC
NC
NC
GND
TOP VIEW
IN
V
CC
OUT
Delay Cap.
6 4 2 1 36 35 34 33 323
7
8
9
10
11
12
13
14 15 16 17 18 19 21 22 23 24
25
26
27
28
29
30
31
20
CCB
interface
Control
circuit
L5 L4 L3 L2 L1
Vref
RVref
LV r ef
LINP RINP LINM RINM LOPOUT ROPOUT VSS CE DI CL VDD
R1 R2 R3 R4 R5
Control
circuit
Logic
circuit
LOUT
LSB
LBASS2
LBASS1
LTRE
LVRIN
LSEL0
ROUT
RSB
RTRE
RVRIN
RSEL0
RBASS2
RBASS1
5