M12L128168A SDRAM (DIGITAL : IC402)
Block Diagram
PIN Functions
Pin Arrangement
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
BA0 , BA1 Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS ,
WE active.
L(U)DQM Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
V
DD
/ V
SS
Power Supply / Ground Power and ground for the input buffers and the core logic.
V
DDQ
/ V
SSQ
Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C No Connection This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Counte
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decoder
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CKE
Command Decoder
CS
RAS
CAS
WE
PIN NAME INPUT FUNCTION
CLK System Clock Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA8
BA0 , BA1 Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low. (Enables row access & precharge.)
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low. (Enables column access.)
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from
CAS , WE active.
L(U)DQM Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input / Output Data inputs / outputs are multiplexed on the same pins.
V
DD
/ V
SS
Power Supply / Ground Power and ground for the input buffers and the core logic.
V
DDQ
/ V
SSQ
Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C No Connection This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Counte
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decoder
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Output
Buffer
Address
Clock
Generator
CLK
CKE
Command Decoder
CS
RAS
CAS
WE
MX25L1606E SERIAL FLASH MEMORY(DIGITAL : IC403)
PCM9211 DIR (DIGITAL : IC432, IC433)
PIN Functions
PIN
DESCRIPTION
NO. NAME I/O
5-V
TOLERANT
1 ERROR/INT0 O No DIR Error detection output / Interrupt0 output
2 NPCM/INT1 O No DIR Non-PCM detection output / Interrupt1 output
3 MPIO_A0 I/O Yes Multipurpose I/O, Group A(1)
4 MPIO_A1 I/O Yes Multipurpose I/O, Group A(1)
5 MPIO_A2 I/O Yes Multipurpose I/O, Group A(1)
6 MPIO_A3 I/O Yes Multipurpose I/O, Group A(1)
7 MPIO_C0 I/O Yes Multipurpose I/O, Group C(1)
8 MPIO_C1 I/O Yes Multipurpose I/O, Group C(1)
9 MPIO_C2 I/O Yes Multipurpose I/O, Group C(1)
10 MPIO_C3 I/O Yes Multipurpose I/O, Group C(1)
11 MPIO_B0 I/O Yes Multipurpose I/O, Group B(1)
12 MPIO_B1 I/O Yes Multipurpose I/O, Group B(1)
13 MPIO_B2 I/O Yes Multipurpose I/O, Group B(1)
14 MPIO_B3 I/O Yes Multipurpose I/O, Group B(1)
15 MPO0 O No Multipurpose output 0
16 MPO1 O No Multipurpose output 1
17 DOUT O No Main output port, serial digital audio data output
18 LRCK O No Main output port, LR clock output
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
ERROR/INT0
NPCM/INT1
MPIO_A0
MPIO_A1
MPIO_A2
MPIO_A3
MPIO_C0
MPIO_C1
MPIO_C2
MPIO_C3
MPIO_B0
MPIO_B1
VDDRX
RXIN1
RST
RXIN2
RXIN3
RXIN4/ASCKIO
RXIN5/ABCKIO
RXIN7/ADIN0
MODE
MS/ADR1
MC/SCL
48 47 46
45
44 43
42
41
40 39 38
13
14
15 16
17
18 19 20
21 22
23
37
24
PCM9211
VINR
VINL
VCCAD
VCOM
FILT
VCC
AGND
XTO
XTI
GNDRX
RXIN0
MPIO_B2
MPIO_B3
MPO0
MPO1
DOUT
LRCK
BCK
SCKO
DGND
DVDD
MDI/SDA
34
Caution in
servicing
Electrical Mechanical Repair Information Updating
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