DH Instruments PPC3 - Standard Event Register; Table 19. 8 Bit Standard Event Register

4. REMOTE OPERATION
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register to 20 ($14 hex), an SRQ will occur if the MAV or the ERROR bit are set.
The description of these bits are given as:
OPER N/A Bit 7 (128)
RQS Requested Service Bit 6 (64)
Indicates that the SRQ line of the IEEE-488 interface has been asserted by the
PPC3. This bit is cleared when a serial poll is performed on the PPC3, and is a
part of the Status Byte Register when read using a serial poll. This bit does not
apply if the COM1 port is being used.
MSS Master Summary Status Bit 6 (64)
Indicates that an event or events occurred that caused the PPC3 to request service
from the Host, much like the RQS bit. Unlike the RQS bit, it is READ ONLY and can
be only cleared when the event(s) that caused the service request are cleared.
ESB Event Summary Bit 5 (32)
Indicates if an enabled bit in the Standard Event Status Register became set
(see Section 4.5.3).
MAV Message Available Bit 4 (16)
Indicates that at least one reply message is waiting in the PPC3 IEEE-488 output
queue.
ERROR Error Queue Not Empty Bit 2 (4)
Indicates that at least one command error message is waiting in the PPC3 IEEE-488
error message queue. Use the “ERR?” query to get this message.
RSR Ready Summary Bit 0 (1)
Indicates that an enabled bit in the Ready Status Register became set.
4.5.3 STANDARD EVENT REGISTER
The PPC3 contains an 8 bit Standard event register that reflects specific PPC3 events.
Enabled events in this register will set or clear the ESB bit of the Status Byte Register.
Table 19. 8 Bit Standard Event Register
PON
(128)
URQ
(64)
CMD
(32)
EXE
(16)
DDE
(8)
QYE
(4)
RQC
(2)
OPC
(1)
This register can be read using the “*ESR?” query, Each of these status bits can set the ESB
bit of the Status Byte Register, causing a SRQ to occur IF the ESB bit is enabled to do so.
The Standard Event Status Enable Register (“*ESE” program message ) determines which of
these flags are able to assert the ESB bit. The description of these bits are given as:
PON Power On (Bit 7)
Indicates that the PPC3 power has been cycled since the last time this bit was
read or cleared.
URQ User Request (Bit 6)
Indicates that the PPC3 was set to local operation manually from the front panel
by the user (pressing the [ESC] key).
CMD Command Error (Bit 5)
Indicates that a remote command error has occurred. A command error is
typically a syntax error in the use of a correct program message.