NZM-XDMI-DPV1
(PROFIBUS-DPV1 Interface for
DMI)
184
11/04 MN01219002Z-EN
Octet 28
1)
Status of the phases L3 and neutral pole
LS_Status[25] Bit 0 Phase L3: Normal range
LS_Status[26] Bit 1 Phase L3: Load rejection prewarning
LS_Status[27] Bit 2 Phase L3: Overload range 1
LS_Status[28] Bit 3 Phase L3: Overload range 2
LS_Status[29] Bit 4 N-pole: Normal range
LS_Status[30] Bit 5 N-pole: Load rejection prewarning
LS_Status[31] Bit 6 N-pole: Overload range 1
LS_Status[32] Bit 7 N-pole: Overload range 2
Octet 29
1)
Tripping phase
LS_Status[33]
Bit 0 Trip via L1
LS_Status[34] Bit 1 Trip via L2
LS_Status[35] Bit 2 Trip via L3
LS_Status[36] Bit 3 Trip via N-pole
LS_Status[37] Bit 4 Circuit-breaker is in the “ON” state
LS_Status[38] Bit 5 Circuit-breaker is in the “OFF” state
LS_Status[39] Bit 6 Circuit-breaker is in the “Tripped” state
LS_Status[40] Bit 7 Normal operation of the circuit-breaker
(communication in order)
Octet 30
1)
Phase issuing alarm
Bit 0 to Bit 3 Not used
LS_Status[45] Bit 4 Alarm from L1
LS_Status[46] Bit 5 Alarm from L2
LS_Status[47] Bit 6 Alarm from L3
LS_Status[48]
Bit 7 Alarm from N-pole
Variable access
(example)
Data position Meaning
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