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ECS KV2 Extreme User Manual

ECS KV2 Extreme
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3-9
Press <Esc> to return to the Advanced Chipset Features page.
strobe). It is recommended that you leave this item at the default value. The
2T setting requires faster memory that specifically supports this mode.
Upstream/Downstream LDT Bus Width (16 bit)
The LDT bus (Lighting Data Transport) is the bus between the North and South
Bridge, and boosts no less that 6.4 GB/sec on a 16 bit upstream and a 16 bit
downstream dataflow.
LDT Bus Frequency (1 GHz)
This option allows you to specify the maximum operating frequency for the LDT
transmitter clock.
PCI/2 Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states, providing
faster data transfer.
PCI/2 Post Write (Enabled)
When enabled, writes from the CPU to PCU bus are buffered, to compensate for
the speed differences between the CPU and PCI bus. When disabled, the writes are
not buffered and the CPU must wait until the write is complete before starting
another write cycle.
PCI Delay Transaction (Disabled)
The motherboard’s chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features page.
VLink Data Rate (8X)
This option allows you to select the data transfer rate between the Northbridge and
Southbridge chipsets.
LDT & PCI Bus Control (Press Enter)
Scroll to this item and press <Enter> to view the following screen:
Upstream LDT Bus Width [16bit]
Downstream LDT Bus Width [16bit]
LDT Bus Frequency [1 GHz]
PCI Master 0 WS Write [Enabled]
PCI2 Master 0 WS Write [Enabled]
PCI Post Write [Enabled]
PCI2 Post Write [Enabled]
PCI Delay Transaction [Disabled]
Item Help

Menu Level
Phoenix-AwardBIOS CMOS Setup Utility
LDT & PCI Bus Control

F5:Previous Values F6:Performance Defaults F7:Optimized Defaults
: Move Enter: Select +/-/PU/PD:Value F10:Save ESC:Exit F1: General Help
RAS# to CAS# delay (Trcd)(Auto)
This item specifies the RAS# to CAS# delay to Rd/Wr command to the same bank.
Min RAS# active time (Tras)(Auto)
This item specifies the minimus RAS# active time.
Row Precharge Time (Trp)(Auto)
This item specifies the Row precharge to Active or Auto-Refresh of the same bank.

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ECS KV2 Extreme Specifications

General IconGeneral
BrandECS
ModelKV2 Extreme
CategoryMotherboard
LanguageEnglish

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