Epson PX-8 - Page 106

REV.-A
2.8.4 Jumper J5
This jumper allows the user to select one of two frame (FR) frequencios. It switches the FR signal
to change the panel display mode. Jumper terminal A (see Fig. 2-84) is wired when the computer
is shipped. Fig. 2-84 shows the FR signal generator circuit which includes the jumper Fig. 2-85 il-
lustrates the timing relationships among various circuit signals.
9a
LP J-6_4 ___ --+_
0
1 A 6
lQO
13 2A
SED
1320
FR 63
2QA j.:.l.:...l_~9_"
2 Q C ~9=--_.::....8 -II
Fig. 2-84 FR Signal Generator Circuit
J5 Jumper
FR
(to LCD unit)
The LP signal is fed to the first stage of the dual 4-bit binary counter, IC 9a. The signal frequency
is divided down to one sixteenth (285 flsec x 16 ...;- 4.5 msec) and is further fed to the second bin-
ary counter. Two outputs are provided from pins 11 (20A) and 9 (2QC) of the second counter,
which respectively have one 32nd and one 1 28th of the original LP signal frequency.
About 285 J.lSec.
LP
9a Pin 6
(1 QD) About 4.5 J1sec.
1QD
2QA
2QC~----------~
2a Pin 10
t-E::------- About 36.4 J1sec.-------~
FR
Fig. 2-85 Timing Relationship Among RF Signal Generator Circuit Signals
2-82