Epson PX-8 - A-D Converter

REV.-A
CI k oc
~RESET
~ RESET
'---
FRC (upper 8 bits)
~
FRC (lower 8 bits)
Overflow
0003 Read
0002 Read
"
7-
,
,.
Main CPU
ICR (upper 8 bits)
ICR (lower 8 bits)
(4A)
r---::
~
0000 Read
j,
Data bus
v
0001 Read
J
L"",,-
I
Trigger mode
~
0000 Write
onverter_ J
Interrupt control I
CTRL
CTRL
I
(IER)
0004 Write
INT
III
A-D c
,.----,
'I'
BRDT
SET
I I
I
ICF (Input Capture Flag) I GAH40D
Interrupt
RESEI
I I
-
L ____ .J
Fig. 2-95 Barcode Data Read Circuit Block Diagram
The barcode data read control is initiated by
an interrupt issued from the gate array
GAH40D to the main CPU. It occurs when
the input capture flag (lCF) is turned ON by a
barcode pattern read (i.e., reader scanning).
The
trigger may be generated at a different
point or points on the pulse, depending on
the BRDT triggering mode selected by the
user. (See Table 2-1 7.)
When interrupted, the main CPU first reads
address
0002 to store the lower eight FRC
bits in the corresponding lower half of ICA.
then
it reads address 0003 to store the upper
Table 2-17 BRDT Triggering Modes
Address 0000
BRDT triggering mode
Bit 1
Bit 0
(polarity)
0 0
Triggering is disabled
0
1
1
Triggering at falling edge
1
0
J
Triggered at rising edge
1
1
Triggered
at both rising
J1
and falling edges
eight FRC bits in the upper half of ICA. and resets ICF, removing the triggering signal. At
the time the trigger pulse is generated, the main CPU reads addresses 0000 and 0001
to determine the FRC count value; ICR maintains this value until it is updated by the next FRC
2-93