REV.-A
2.12
Serial
Interface
This interface is provided
by
using
the
serial
port
of
the
6303
slave CPU. A baud rate is obtained
by
dividing
the
614
kHz system
clock
supplied
from
the
6303
according
to
the
command
sent
from
the main
CPU.
IFig.
2-112
is a
circuit
diagram
of
the
serial interface.
___
1;..;::9:-1
P
16
~--,-,8'-tPI5
.--
__
-+-_--'-17'-1
P
14
Slave
CPU
6303
..-----+--"-'-1
P
23
..-----'-'.....
P 24
E
1
2
(INHRS)
Q
18
Collector
-+-+-----1r--1>L----;
SERIAL
CN6
POUT
7
PRX
3
PIN
6
Fig.
2-112
Serial
Interface
Circuit
2.12.1
Power
Supply
The
driver
(12C) and receiver (9B) circuits in
this
interface are
the
same as
those
used in
the
RS-232C interface. Thus,
the
same ±
8V
voltage regulator is required,
which
is
also
controlled
by
the gate array
GAH40M.
See paragraph 2.5.3
for
details
of
the
regulator operation.
2.12.2
Data
Transmission
Rate
A baud rate can be determined
by
varying
the
internal frequency division
of
the
clock
signal
to
the
slave
CPU
(2.4576
MHz). One
of
four
baud rates,
38.4K,
4800,
600,
and
150
bps, can be select-
ed. The baud rate selection is accomplished
by
rewriting
slave
CPU
address
0010
(the Slave
CPU
transmission
rate/mode
control
register)
as
shown
in Table
2-21.
(The original frequency
of
2.4576
MHz is quartered
within
the
slave
CPU
to
the
614
kHz operating
clock
signaL)
Table
2-21
Option
Unit
Data
Transmission
Rate
Selection
Address
0000
Frequency Division Ratio (Frequency
Transmission Rate
Bit 1
BitO
Division
to
the Operation Clock Signal)
0 0
1/16
26.us
34800
bauds
0
1
1/128
208.us
4800
bauds
1
0
1/1024
1.67ms
600
bauds
1 1
1/4096
6.67ms
150
bauds
2-108
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