Epson PX-8 - LCD;V-RAM Controllersed1320

REV.-A
r 7.11 LCD/V-RAM Controller SED1320
The gate array is the LCD driver controller which displays the LCD panel using a 6kB external V-
RAM. It also provides the interface between the main and slave CPUs and the character genera-
tion capability
for LCD display. Fig. 7-21 is a functional block diagram of SED 1 320.
External
4.9M ____ ~ 1/2 divider I---..----------------clock signal
(GAH40D) circuit
to 6303
PDO ~ 7
PAO
PRD -+---------l~
PVVR--------+--+--~
DMA
X,V
count/
ddress V clock
comman~ signal
Character
generator
I..--r-r---l I I L.r-r--~
LAO ~ 12
FR, LP LVVE LCD data
XSCL
XDO ~ 3
VSCL
XECL
VSPU
ADO ~ 7
1------- R/VV
Decoder
Data
~
AS
I
~E
I
I
I
A8 ~ A12
DO ~ 7 Address LCSE1 ~ 3
AO ~12
Fig.7-21 SED1320 Gate Array Functional Block Diagram
7-50