Epson PX-8 - Page 322

REV.-A
7.11.1 LCD/V-RAM Control
This gate array incorporates registers for controlling the screen pointer, etc. as well as a 1/2 clock
frequency divider which generates the LCD clock signal from the 4.9 MHz input clock signal. The
screen
control is accomplished by a procedure in which the slave CPU 6303 sends commands/
data to SED1320; the SED1320 responds with one-byte return codes.
V-RAM read/write is accomplished by the slave CPU. Data transfer to the LCD drivers is made via
the DMA controller incorporated in the SED 1320.
Displayed text character fonts are generated by the incorporated character generator. The used
character
set is determined by the DIP SW4 setting which anyone of the international character
sets. The switch is read at initialization.
7.11.2 Communications Between Main And Slave CPUs
When the main CPU sends a command or data to the PDIR register, the SINT signal interrupts the
slave CPU via the gate array GAH40S (lNTR signal). The slave CPU reads the command/data by
setting the interrupt mask register in GAH40S. When data is transferred from the slave to the
main CPU, the slave CPU deposits the data to the POOR register which is read by an I/O read from
the main CPU. In either direction of transfer, a handshake can be established between the two
CPUs in which the CPUs can examine the state of the port data register PDIR/PDOR through a
port status change or register (PSR) and control status register (CSR).
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