Epson PX-8 - ROM Capsule

REV.-A
2.10 ROM Capsule
The ROM capsule can hold two 256kB ROMs and is controlled by the gate array GAH40S. A
power supply line which generates and supplies +5V power from the VB line to the capsule, as re-
quired, is also included in the circuit. Fig. 2-98 is a block diagram of the ROM capsule and its con-
trol and data lines and buses.
~
-
0
OJ
...
OJ
0
I
-...J
-
-
-
~
;-
apsule
ROMe
powr(+
5V) supply
2.10.1 Addressing
A
9E
~
ROM #2
(OOOOH ~ 7FFFH)
~
A
10E
~.-
ROM #1
(8000H ~ FFFFH)
~
C C
GAH40S
S
S
P
P
1
0
~>. I
1\ I 1\ /
1\ t!
DAO ~ 7
Fig. 2-98
:l>
0..
0..
.,
CD
en
en
0
I
~
6303
oj:>.
(130)
AB14
AB15
E
AS
R/W
~
V
Two 2767 (8kB), 27128 (16kB), or 27256 (32kB) ROM can be mountedto the ROM capsule and
are accessed via the 6303 slave CPU as follows:
The ROMs are addressed using the data address lines DAO through DA7. An address is therefore
set in GAH40S in two parts. GAH40S has two 8-bit PROM address registers; High and Low,
which can be directly accessed as an I/O address from the slave CPU.
The most significant bit (MSB) of this set of address registers is used to select either ROM # 1 or
# 2 (i.e., serves as the chip select bit). Fig. 2-99 is a block diagram conceptually illustrating ROM
capsule addressing.
2-96