Epson PX-8 - Dynamic RAM

REV.-A
2.14 Dynamic RAM
As shown in Fig. 2-11 7, eight address lines, one data input, and one output line are connected to
---- -
the D-RAM, which is controlled by four signals; W, RAS, CAS, and RF.
-\
~
00
Output
~
AO ~ 7
N
i
.-
~
buffer
IV'
~
....
Q)
-V
"0
Cell matrix
0
Input
i
u
Q)
buffer
"0
DO
~
r---
~
0
L
a:
Timing pulse
generator
f-o
w
II
circuit
-\
Column decoder (128)
~
~
11'
DI
RAS
Row
timing pulse Column timing pulse
"
generator circuit
generator circuit
...,
CAS
'---
Refresh address counter
I
Refresh controller
-0
RF
Fig. 2-117 D-RAM Control Functional Block Diagram
< Address lines>
Each D-RAM chip has a capacity of 64k bits, permitting only eight lines to be addressed at a time.
Therefore,
GAH40D sends the upper and lower eight bits of the 16 bit address lines from the main
CPU separately. This adress mode is illustrated in Fig. 2-118.
16 address
lines
-\
Main
CPU
-V
8 address
lines
GAH40D
-l\
Fol
I
v'
IA7
I
--
lAB
I
(
~5J
Address decoder
~l
?
A7 I
fAa-
2 I
~5J
Address output
from main CPU
GAH40D
address decoder
RAS
..... --'
Q)
CAS~----~
Fig. 2-118 D-RAM Addressing Control
2-114