Epson PX-8 - Page 139

REV.-A
2.14.1 O-RAM Accesses
The O-RAM is read/written and refreshed via the gate array GAH400. The O-RAM is a quasi
C-MOS
product (the output section is built with C-MOS and the internal circuitry uses N-MOS),
which requires a relatively large amount of operating current. Consequently, a power-saving fea-
ture is provided,
which selects a minimum safe refresh current, depending on ambient tempera-
ture.
I
Address line 0 ~ 7
vJ~ vJ~
vJ
(7E)
(60)
(6E)
(70)
OW
(6A)
-
~
Q
~
1:1
~
Q
RF
Bit 6
Bit 4
Bit 2
BitO
I--
OCAS -
~
GAH400
W
-
RAS
Vl
l.l\
Vl
l.l\
Vl
l.l\
I Bank I
CAS
(50)
(4F) (5E)
(40)
control
Bit 7
1~r
Bit 5
1~r
Bit 3
1~r
Bit 1
1
,
I
,
•
Data bus 0 ~ 7
I~
Main CPU
GAH40M
I--
IPL
ROM
, r
Bank 0
L~CTLR REG ~.J
.--
LJ--lJ----------l
-
Option unit (RAM disk)
BK2
I
!-GAH400:
64KB/128KB
I
I
I
~ ______ .J
______________ J
Sub CPU 7508
I
Fig.2-119 O-RAM Configuration
An external 64kB or 128kB O-RAM memory can be expanded as an option unit. which can also be
battery-backed up, as
shown in Fig. 2-119; the refresh signals OW and OCAS are also supplied
from the sub-CPU 7508 to the option unit.
2-115