Epson PX-8 - Page 122

This power supply is controlled using a 3-second timer and operates as follows:
(1) When power is off
REV.-A
The SWPR signal enables the voltage regulator. 50 ms later, ROM is read and the timer is trig-
gered.
(2)
When power is already on
ROM is read and
the timer is triggered.
The above
3-second timer is used to enable the voltage regulator only during ROM read; the regu-
lator is automatically disabled if ROM is not read within three seconds. ROM access is made effi-
cient in cases where many ROM reads are repeated within a short period of time by eliminating
the 50 ms wait time required for regulator stabilization. Fig. 2-101 illustrates an outline of the re-
gulator control.
ROM read
R,g,'otoe o",p",~ :
---l1~0 ms
I
Hi,
f..----l
-1~ms~ ~~ms
3 second
.3 second
Fig. 2-101 ROM Power Voltage Regulator Control
2.10.3 ROM Data Format
It should be noted that the logical addresses
(memory addresses as seen from the main CPU)
and
the actual ROM addresses do not com-
pletely match, as shown in Table 2-18. Logical
addresses are used in
the following descrip-
tions on ROM data format.
2-98
Logical
address
0000
)
3FFF
4000
)
7FFF
Table 2-18
ROM Address
2764 27128
(8 kB)
(16 kB)
0000
0000
)
1 FFF
I
I
H
3 second
27256
(32 kB)
4000
~
7FFF
0000
)
3FFF