Epson PX-8 - Page 127

REV.-A
2.11.2.2. Data Read/Write
A read/write at I/O address OC or 00 from the main CPU causes the Chip Select (CS) signal and
the Read (RO) or Write (WR) signal to be issued from the address decoder circuit in GAH40H. An
I/O address ABO is connected to pin 20 and dealt with as the C/O signal.
Thus, address
00 is used as the command address of the 82C51 and address OC is used as the
data address. Fig. 2-105 is a block diagram illustrating the read/write control flow.
Main CPU
Address bus
<
'oj
D
R
W
lOR
R
Q
..
v
..
...
.-
.-
GAH40M
oc
Address decoder
IR
R/W control
IW
ABO
C/D
Fig. 2-105
82C51
'~C'
~
....
Data buffer
.-
y-
f------
Receive
Transmit
,
It-
T
I
,/L-
Control register
y-
...
,
'OD'
I-
Data bus
* The transmit and receive buffers can hold only one byte each. Thus, the main CPU transfers
data
byte by byte.
2.11.2.3 Interfacing
The RS-232C and option unit signal lines are connected to the transmit and receive signal lines
(RXO and TXO) and
their input and output are controlled by the 82C51. To prevent the two in-
put/output signals from interfering with each other, the input/output of the RS-232C signals is
enabled and disabled by
the AUX signal from GAH50M (which can be controlled by bit 5 of I/O
address 02). Fig.
2-106 shows the control circuit.
9
82C51
RXD
1 1
3
8
RXD
RS-232C
(2C)
4
RXD J Option unit
AUX
TXD
TXD
5
19
TXD
Fig. 2-106 RS-232C RXD and TXD Line Control Circuit
2-103