Epson PX-8 - Page 273

REV.-A
7.1.3 Timing
An instruction is normally executed in combination with one of the following three basic machine
cycles:
(1)
Instruction op code fetch (MI cycle)
(2)
Memory read/write cycle
(3)
Input/output cycle
* The relation between clock, state and machine cycle is as follows.
1 state = 1 clock
1 machine cycle = 3 to 6 states
1 instruction cycle = 2 to 6 machine cycles
7.1.4 Interrupt Function
The NMI (non maskable interrupt) line of the main CPU cannot be used because it is always pulled
up
by resistor R94. Therefore, only the maskable interrupt INTR line is valid in this machine. The
interrupt function operates in one of the following three modes:
Mode 0: Executes the instruction (normally RST or CALL) read in MI (mode condition after reset).
Mode 1: Saves the content of the program counter and automatically causes a branch to 0038H.
Mode 2: Executes an indirect CALL instruction according to the content of the index registor and
the data which has been read.
* These interrupts may not be accepted when the BUAK signal is low. (I.C., that period when the
CPU is keeping the bus open).
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