Epson PX-8 - Page 282

REV.-A
Pin No.
Signal Name
In/Out Function
15
P71
Out Data write - prevents FF latches in gate array
at power off.
16
P72
Out Data write - D-RAM refresh control signal
during power off.
17
P73
Out Data CAS
18
RS In
Reset signal
input
19
CL 1 In
Clock signal
input
20 VC
In
+5V (Battery voltage: VB) terminal
22 CL2
In Clock signal
input
23
POO/INTO In POWER switch
--
24
SCK
Out Shift clock signal output - used for A-D con-
version data/main CPU command read.
25
SO Out Serial data output
26
SI In
Serial data
output
27
P60 In
RESET switch
28
P61 In Charge start detection
29 P62 In
Analog interface trigger input
30 P63
In Test point
31
P50 In Key return 4
32 P51 In
Key return 5
33 P52 In Key return 6
34
P53 In Key return 7
35
P40
Out Reset signal - initializes main CPU and slave
CPU, etc. via
GAH40.
36 P41
Out Charge mode control- normal/trickle charge.
37
P42
Out
Auxiliary battery backup enable/disable con-
trol.
38
P43
Out Interrupt to main CPU
39 G In Ground terminal
40 X1
In External clock signal input - 1 kHz
7-11