Epson PX-8 - Page 316

REV.-A
On Y drive lines, data transferred in serial is included in the shift register bit by bit according to
YSCL signals (shift clock). Then, Y drive signals corresponding to these data are output. Data
transfer timing is shown in Fig. 7-20.
Approx. 285 I1sec.
YSCL 1-------'
DIN
~ D63
X
D64
X
DO
LP~------------~
1
n n
SPUI----------------'
FR ~--------------___f
1 6.64 msec. (260 I1sec. x 64)
Fig. 7-20
When a YSCL signal is output, DIN is included in the internal shift register, an LP signal latches
the content of the shift register, and the latched data is output on the Y drive line.
7-45