REV.-A
• Power off:
P70
of
the
sub-CPU
going
high, causes
the
output
of
pin
14
of
inverter,
120, to
go
high,
turning
06
off
and thereby
stopping
the
logic
circuit
voltage supply.
023
is
controlled
by
the
sub-CPU, via P42, returning
it
to
the
normal backup operation.
•
When
the
power-off
request is an interrupt, generated
when
the
POWER
switch
is turned
OFF
or
low
voltage is detected.
When
the
power
is turned
Off
and
the
power
off
request is
comitted,
the current operation has
to
be examined and a sequence excuted
which
assures
that
the
oper-
ation in progress, including any I/O operation sequence,
will
be resumed
without
error
when
power
is restored. The sequence
allows
all necessary processes such
as
the
reinitialization
of
the
I/O device (e.g., microcassette) in operation, a
warning
message display, etc.
to
be
accom-
plished before
the
logic
circuit
voltage supply is actually removed.
•
OFF
signal: The
OFF
signal
shown
in Fig.
2-5
is controlled via
P71
of
sub-CPU
7508.
This sig-
nal is
emitted
to
gate arrays
6A
and 4C, and
the
expansion interface CN8.
It
is intended
to
ini-
tialize
the
internal
circuit
of
the
gate arrays in order
to
prevent
their
outputs
from
being latched;
it
is a so called reset signal
to
the
gate arrays and does
not
control
power
supply
to
the
gate ar-
rays.
The relationship between
P70
and P42
of
sub-CPU
7508
will
be discussed in section 2.3,
"Low
Voltage Detection".
2-9
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